remove host core generation

strip config.json emitted by raptor
add actual pimsim-nn configs in validation pimsim-configs

src/PIM/Compiler/PimArtifactWriter.cpp

@@ -20,38 +20,6 @@ using namespace mlir;
 
 namespace onnx_mlir {
 
-OnnxMlirCompilerErrorCodes writeHostCoreArtifacts(StringRef outputDirPath) {
-  std::error_code errorCode;
-  std::string outputHostCorePath = outputDirPath.str() + "/core_0.pim";
-  raw_fd_ostream hostFileStream(outputHostCorePath, errorCode, sys::fs::OF_None);
-  if (errorCode) {
-    errs() << "Error while opening host core file `" << outputHostCorePath << "`: " << errorCode.message() << '\n';
-    return InvalidOutputFileAccess;
-  }
-
-  pim_binary::writeHeader(hostFileStream);
-  pim_binary::InstructionRecord noop;
-  noop.opcode = pim_binary::Opcode::sldi;
-  pim_binary::writeInstructionRecord(hostFileStream, noop);
-  pim_binary::writeInstructionRecord(hostFileStream, noop);
-  pim_binary::patchInstructionCount(hostFileStream, 2);
-  hostFileStream.close();
-
-  if (pimEmitJson.getValue()) {
-    std::string outputHostJsonPath = outputDirPath.str() + "/core_0.json";
-    raw_fd_ostream hostJsonStream(outputHostJsonPath, errorCode);
-    if (errorCode) {
-      errs() << "Error while opening host core json file `" << outputHostJsonPath << "`: " << errorCode.message()
-             << '\n';
-      return InvalidOutputFileAccess;
-    }
-    // The host core json contains two no-op-like instructions to satisfy pimsim-nn
-    hostJsonStream << "[{\"imm\":0,\"op\":\"sldi\",\"rd\":0},{\"imm\":0,\"op\":\"sldi\",\"rd\":0}]";
-    hostJsonStream.close();
-  }
-  return CompilerSuccess;
-}
-
 OnnxMlirCompilerErrorCodes
 writeMemoryBinary(ModuleOp moduleOp, func::FuncOp funcOp, PimAcceleratorMemory& memory, StringRef outputDirPath) {
   auto memoryFilePath = (outputDirPath + "/memory.bin").str();
@@ -109,9 +77,6 @@ OnnxMlirCompilerErrorCodes writeConfigJson(func::FuncOp funcOp,
   json::Object configJson;
 
   configJson["core_cnt"] = maxCoreId + 1;
-  configJson["adc_count"] = 16;
-  configJson["cell_precision"] = 2;
-  configJson["xbar_array_count"] = crossbarCountInCore.getValue();
   configJson["xbar_size"] = {crossbarSize.getValue(), crossbarSize.getValue()};
   configJson["array_group_map"] = std::move(xbarsPerArrayGroup);
 

src/PIM/Compiler/PimArtifactWriter.hpp

@@ -12,7 +12,6 @@ namespace onnx_mlir {
 
 class PimAcceleratorMemory;
 
-OnnxMlirCompilerErrorCodes writeHostCoreArtifacts(llvm::StringRef outputDirPath);
 OnnxMlirCompilerErrorCodes writeMemoryBinary(mlir::ModuleOp moduleOp,
                                              mlir::func::FuncOp funcOp,
                                              PimAcceleratorMemory& memory,

src/PIM/Compiler/PimCodeGen.cpp

@@ -875,11 +875,6 @@ OnnxMlirCompilerErrorCodes onnx_mlir::compileToPimCode(ModuleOp& moduleOp, std::
   if (auto err = writeMemoryBinary(moduleOp, funcOp, memory, outputDirPath))
     return err;
 
-  if (auto err = writeHostCoreArtifacts(outputDirPath))
-    return err;
-
-  // For each core, specify the number of crossbar per array group.
-  // This implementation always assigns one crossbar per group.
   json::Object xbarsPerArrayGroup;
   size_t maxCoreId = 0;
   uint64_t nextBatchReportId = 0;
@@ -891,7 +886,7 @@ OnnxMlirCompilerErrorCodes onnx_mlir::compileToPimCode(ModuleOp& moduleOp, std::
   SmallDenseMap<memref::GlobalOp, MemEntry, 16> materializedHostGlobals =
     collectMaterializedHostGlobals(moduleOp, funcOp, memory);
   llvm::DenseMap<size_t, size_t> emittedCoreIds;
-  size_t nextEmittedCoreId = 1;
+  size_t nextEmittedCoreId = 0;
 
   for (Operation* op : coreLikeOps) {
     if (auto coreOp = dyn_cast<pim::PimCoreOp>(op)) {