finally fast googlenet with correct latency artifacts for fair comparison
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Validate Operations / validate-operations (push) Has been cancelled
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NiccoloN
@@ -1,9 +1,21 @@
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#include "mlir/Conversion/AffineToStandard/AffineToStandard.h"
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#include "mlir/Transforms/Passes.h"
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#include "llvm/Support/Error.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/JSON.h"
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/Support/Path.h"
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#include "llvm/ADT/SmallString.h"
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#include <cmath>
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#include <limits>
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#include <tuple>
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#include "src/Accelerators/PIM/Compiler/PimCompilerOptions.hpp"
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#include "src/Accelerators/PIM/Compiler/PimCompilerUtils.hpp"
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#include "src/Accelerators/PIM/Dialect/Pim/PimOps.hpp"
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#include "src/Accelerators/PIM/Dialect/Spatial/Transforms/MergeComputeNodes/Scheduling/SchedulingTarget.hpp"
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#include "src/Accelerators/PIM/Pass/PIMPasses.h"
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#include "src/Compiler/CompilerPasses.hpp"
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@@ -14,6 +26,254 @@ using namespace onnx_mlir;
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namespace onnx_mlir {
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namespace {
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void setDefaultPimInterProcessorLatencies(
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spatial::SchedulingTarget& target) {
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size_t rows = static_cast<size_t>(
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std::sqrt(static_cast<long double>(target.processorCount)));
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while (rows > 1 && target.processorCount % rows != 0)
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--rows;
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size_t columns = (target.processorCount + rows - 1) / rows;
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target.interProcessorLatencyNs.assign(
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target.processorCount * target.processorCount, 0);
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Cost latencySum = 0;
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size_t pairCount = 0;
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for (size_t source = 0; source < target.processorCount; ++source) {
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for (size_t destination = 0;
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destination < target.processorCount; ++destination) {
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if (source == destination)
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continue;
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size_t sourceRow = source / columns;
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size_t sourceColumn = source % columns;
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size_t destinationRow = destination / columns;
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size_t destinationColumn = destination % columns;
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size_t rowDistance = sourceRow > destinationRow
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? sourceRow - destinationRow
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: destinationRow - sourceRow;
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size_t columnDistance = sourceColumn > destinationColumn
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? sourceColumn - destinationColumn
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: destinationColumn - sourceColumn;
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Cost latency = static_cast<Cost>(2 + rowDistance + columnDistance);
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target.interProcessorLatencyNs[
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source * target.processorCount + destination] = latency;
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latencySum = checkedAdd(latencySum, latency);
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++pairCount;
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}
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}
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target.averageInterProcessorLatencyNs =
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pairCount == 0
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? 0
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: (latencySum + static_cast<Cost>(pairCount) - 1)
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/ static_cast<Cost>(pairCount);
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}
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spatial::SchedulingTarget getDefaultPimSchedulingTarget() {
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spatial::SchedulingTarget target;
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target.processorCount = static_cast<size_t>(coresCount.getValue());
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target.residentWeightCapacity = crossbarCountInCore.getValue();
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target.matrixRows = crossbarSize.getValue();
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target.matrixColumns = crossbarSize.getValue();
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setDefaultPimInterProcessorLatencies(target);
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return target;
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}
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const llvm::json::Object& requireObject(const llvm::json::Object& object,
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llvm::StringRef key,
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llvm::StringRef path) {
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const llvm::json::Object* nested = object.getObject(key);
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if (!nested)
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llvm::report_fatal_error("PIM target config is missing object '" + path + "." + key + "'");
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return *nested;
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}
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Cost getConfigCost(const llvm::json::Object& object,
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llvm::StringRef key,
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Cost fallback,
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bool allowZero = false) {
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std::optional<double> number = object.getNumber(key);
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if (!number)
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return fallback;
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if (!std::isfinite(*number) || *number < 0.0 || (!allowZero && *number == 0.0)
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|| *number > static_cast<double>(std::numeric_limits<Cost>::max()))
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llvm::report_fatal_error("PIM target config field '" + key + "' must be a valid positive number");
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return static_cast<Cost>(std::ceil(*number));
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}
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std::pair<size_t, size_t> getConfigPair(const llvm::json::Object& object,
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llvm::StringRef key) {
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const llvm::json::Array* values = object.getArray(key);
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if (!values || values->size() != 2)
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llvm::report_fatal_error("PIM target config field '" + key + "' must contain two integers");
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std::optional<int64_t> first = (*values)[0].getAsInteger();
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std::optional<int64_t> second = (*values)[1].getAsInteger();
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if (!first || !second || *first <= 0 || *second <= 0)
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llvm::report_fatal_error("PIM target config field '" + key + "' must contain two positive integers");
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return {static_cast<size_t>(*first), static_cast<size_t>(*second)};
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}
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void loadPimInterProcessorLatencies(
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spatial::SchedulingTarget& target,
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const llvm::json::Object& network) {
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std::optional<llvm::StringRef> filename =
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network.getString("net_config_file_path");
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if (!filename)
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llvm::report_fatal_error(
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"PIM target config is missing network latency file path");
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llvm::SmallString<256> networkPath(*filename);
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if (!llvm::sys::path::is_absolute(networkPath)) {
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llvm::SmallString<256> configDirectory(pimTargetConfig.getValue());
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llvm::sys::path::remove_filename(configDirectory);
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llvm::sys::path::append(configDirectory, networkPath);
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networkPath = configDirectory;
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}
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auto buffer = llvm::MemoryBuffer::getFile(networkPath);
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if (!buffer)
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llvm::report_fatal_error(
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llvm::Twine("failed to read PIM network config '")
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+ networkPath + "': " + buffer.getError().message());
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auto parsed = llvm::json::parse(buffer.get()->getBuffer());
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if (!parsed)
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llvm::report_fatal_error(
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llvm::Twine("failed to parse PIM network config '")
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+ networkPath + "': " + llvm::toString(parsed.takeError()));
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const llvm::json::Object* root = parsed->getAsObject();
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const llvm::json::Object* latencies =
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root ? root->getObject("latency") : nullptr;
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if (!latencies)
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llvm::report_fatal_error(
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"PIM network config is missing its latency matrix");
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target.interProcessorLatencyNs.assign(
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target.processorCount * target.processorCount, 0);
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Cost latencySum = 0;
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size_t pairCount = 0;
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for (size_t source = 0; source < target.processorCount; ++source) {
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std::string sourceKey = std::to_string(source);
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const llvm::json::Object* row = latencies->getObject(sourceKey);
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if (!row)
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llvm::report_fatal_error(
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llvm::Twine("PIM network config is missing latency row ")
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+ sourceKey);
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for (size_t destination = 0;
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destination < target.processorCount; ++destination) {
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if (source == destination)
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continue;
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std::string destinationKey = std::to_string(destination);
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std::optional<double> latency = row->getNumber(destinationKey);
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if (!latency || !std::isfinite(*latency) || *latency <= 0.0)
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llvm::report_fatal_error(
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llvm::Twine("PIM network config is missing latency ")
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+ sourceKey + " -> " + destinationKey);
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Cost roundedLatency = static_cast<Cost>(std::ceil(*latency));
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target.interProcessorLatencyNs[
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source * target.processorCount + destination] = roundedLatency;
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latencySum = checkedAdd(latencySum, roundedLatency);
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++pairCount;
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}
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}
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target.averageInterProcessorLatencyNs =
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pairCount == 0
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? 0
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: (latencySum + static_cast<Cost>(pairCount) - 1)
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/ static_cast<Cost>(pairCount);
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}
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spatial::SchedulingTarget getPimSchedulingTarget() {
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spatial::SchedulingTarget target = getDefaultPimSchedulingTarget();
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if (pimTargetConfig.empty())
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return target;
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auto buffer = llvm::MemoryBuffer::getFile(pimTargetConfig);
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if (!buffer)
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llvm::report_fatal_error(
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llvm::Twine("failed to read PIM target config '")
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+ pimTargetConfig.getValue() + "': " + buffer.getError().message());
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auto parsed = llvm::json::parse(buffer.get()->getBuffer());
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if (!parsed)
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llvm::report_fatal_error(
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llvm::Twine("failed to parse PIM target config '")
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+ pimTargetConfig.getValue() + "': "
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+ llvm::toString(parsed.takeError()));
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const llvm::json::Object* root = parsed->getAsObject();
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if (!root)
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llvm::report_fatal_error("PIM target config must contain a JSON object");
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const llvm::json::Object& chip = requireObject(*root, "chip_config", "root");
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const llvm::json::Object& core = requireObject(chip, "core_config", "chip_config");
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const llvm::json::Object& matrix =
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requireObject(core, "matrix_config", "chip_config.core_config");
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const llvm::json::Object& localMemory =
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requireObject(core, "local_memory_config", "chip_config.core_config");
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const llvm::json::Object& network =
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requireObject(chip, "network_config", "chip_config");
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std::optional<int64_t> coreCount = chip.getInteger("core_cnt");
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if (!coreCount || *coreCount <= 0)
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llvm::report_fatal_error("PIM target config field 'core_cnt' must be a positive integer");
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target.processorCount = static_cast<size_t>(*coreCount);
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target.residentWeightCapacity =
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getConfigCost(matrix, "xbar_array_count", target.residentWeightCapacity);
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std::tie(target.matrixRows, target.matrixColumns) =
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getConfigPair(matrix, "xbar_size");
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if (target.processorCount != static_cast<size_t>(coresCount.getValue())
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|| target.residentWeightCapacity != crossbarCountInCore.getValue()
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|| target.matrixRows != crossbarSize.getValue()
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|| target.matrixColumns != crossbarSize.getValue())
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llvm::report_fatal_error("PIM target config resources do not match --core-count, "
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"--crossbar-count, and --crossbar-size");
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loadPimInterProcessorLatencies(target, network);
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target.processorPeriodNs =
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getConfigCost(core, "period", target.processorPeriodNs);
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target.localMemoryWidthBytes =
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getConfigCost(localMemory, "data_width", target.localMemoryWidthBytes);
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target.localMemoryReadLatencyCycles =
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getConfigCost(localMemory, "read_latency_cycle", target.localMemoryReadLatencyCycles);
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target.localMemoryWriteLatencyCycles =
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getConfigCost(localMemory, "write_latency_cycle", target.localMemoryWriteLatencyCycles);
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target.transferWidthBytes =
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getConfigCost(network, "bus_width", target.transferWidthBytes);
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target.vectorWidth = getConfigCost(core, "vector_width", target.vectorWidth);
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target.vectorLatencyCycles =
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getConfigCost(core, "vector_latency_cycle", target.vectorLatencyCycles);
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target.matrixPeriodNs =
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getConfigCost(matrix, "period", target.matrixPeriodNs);
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target.matrixInputResolutionBits =
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getConfigCost(matrix, "dac_resolution", target.matrixInputResolutionBits);
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target.matrixInputLatencyCycles =
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getConfigCost(matrix, "dac_latency_cycle", target.matrixInputLatencyCycles);
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target.matrixInputParallelism =
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getConfigCost(matrix, "dac_count", target.matrixInputParallelism);
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target.matrixReadLatencyNs =
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getConfigCost(matrix, "xbar_latency", target.matrixReadLatencyNs);
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target.matrixSampleLatencyCycles =
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getConfigCost(matrix, "sample_hold_latency_cycle", target.matrixSampleLatencyCycles);
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target.matrixOutputLatencyCycles =
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getConfigCost(matrix, "adc_latency_cycle", target.matrixOutputLatencyCycles);
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target.matrixOutputParallelism =
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getConfigCost(matrix, "adc_count", target.matrixOutputParallelism);
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target.matrixShiftLatencyCycles =
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getConfigCost(matrix, "shift_adder_latency_cycle", target.matrixShiftLatencyCycles);
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target.matrixBufferLatencyCycles =
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getConfigCost(matrix, "output_buffer_latency_cycle", target.matrixBufferLatencyCycles);
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target.matrixInputBufferLatencyCycles =
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getConfigCost(matrix,
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"input_buffer_latency_cycle",
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target.matrixInputBufferLatencyCycles,
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/*allowZero=*/true);
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target.matrixPipeline = matrix.getBoolean("pipeline_mode").value_or(target.matrixPipeline);
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return target;
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}
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} // namespace
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void addPassesPim(OwningOpRef<ModuleOp>& module,
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PassManager& pm,
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EmissionTargetType& emissionTarget,
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@@ -31,11 +291,13 @@ void addPassesPim(OwningOpRef<ModuleOp>& module,
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addONNXToMLIRPasses(pm, /*target CPU*/ false);
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if (pimEmissionTarget >= EmitSpatial) {
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spatial::SchedulingTarget schedulingTarget = getPimSchedulingTarget();
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pm.addPass(createONNXToSpatialPass());
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pm.addPass(createSpatialLayoutPlanningPass());
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pm.addPass(createLowerSpatialPlansPass());
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pm.addPass(createTrivialGraphComputeMergePass());
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pm.addPass(createMergeComputeNodesPass());
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pm.addPass(createTrivialGraphComputeMergePass(
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schedulingTarget.residentWeightCapacity));
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pm.addPass(createMergeComputeNodesPass(schedulingTarget));
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pm.addPass(createMessagePass("Onnx lowered to Spatial"));
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}
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