diff --git a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs index f70186e..1361477 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs @@ -1,25 +1,29 @@ #![allow(unused)] +use std::time::{Duration, SystemTime}; + use crate::{ - cpu::CPU, instruction_set::{Instruction, InstructionStatus, Instructions, isa::functor_to_name}, memory_manager::type_traits::TryToUsize, send_recv::{SendRecv, handle_send_recv}, tracing::TRACER + cpu::CPU, + instruction_set::{Instruction, InstructionStatus, Instructions, isa::functor_to_name}, + memory_manager::type_traits::TryToUsize, + send_recv::{SendRecv, handle_send_recv}, + tracing::TRACER, }; pub mod cpu; pub mod instruction_set; +pub mod json_to_instruction; pub mod memory_manager; pub mod send_recv; -pub mod utility; -pub mod json_to_instruction; pub mod tracing; - - +pub mod utility; #[derive(Debug, Clone)] pub struct CoreInstructionsBuilder { - core_instructions : Vec + core_instructions: Vec, } impl CoreInstructionsBuilder { - pub fn new(size:usize) -> Self { + pub fn new(size: usize) -> Self { let mut core_instructions = Vec::with_capacity(size); for _ in 0..=size { core_instructions.push(CoreInstruction::empty()); @@ -31,13 +35,13 @@ impl CoreInstructionsBuilder { self.core_instructions } - pub fn set_core(&mut self, core : impl TryToUsize, core_instruction : Instructions) -> &mut Self{ - self.core_instructions[core.try_into().expect("Set core with not valid size")] = core_instruction.into(); - self + pub fn set_core(&mut self, core: impl TryToUsize, core_instruction: Instructions) -> &mut Self { + self.core_instructions[core.try_into().expect("Set core with not valid size")] = + core_instruction.into(); + self } } - #[derive(Debug, Clone)] pub struct CoreInstruction { instructions: Instructions, @@ -53,7 +57,10 @@ impl CoreInstruction { } fn empty() -> Self { - Self { instructions: Vec::new(), program_counter: 0 } + Self { + instructions: Vec::new(), + program_counter: 0, + } } } @@ -70,36 +77,59 @@ impl From for CoreInstruction { pub struct Executable<'a> { cpu: CPU<'a>, core_instructions: Vec, - send_recv : SendRecv, + send_recv: SendRecv, +} + +fn print_status(core_instructions: &[CoreInstruction]) { + for (i, core_instruction) in core_instructions.iter().enumerate() { + println!( + "Core {} : {}% ({}/{}) ", + i, + core_instruction.program_counter as f32 / core_instruction.instructions.len() as f32 + * 100.0, + core_instruction.program_counter, + core_instruction.instructions.len() + ) + } + + println!(); } impl<'a> Executable<'a> { pub fn new(cpu: CPU<'a>, core_instructions: Vec) -> Executable<'a> { let num_core = cpu.num_core(); let send_recv = SendRecv::new(num_core); - assert_eq!(num_core, core_instructions.len(), "Some core doesn't have is list of istruction (required even if empty)"); + assert_eq!( + num_core, + core_instructions.len(), + "Some core doesn't have is list of istruction (required even if empty)" + ); Self { cpu, core_instructions, - send_recv + send_recv, } } - pub fn execute<'b>(&'b mut self) - where 'a : 'b + pub fn execute<'b>(&'b mut self) + where + 'a: 'b, { let Self { - cpu , + cpu, core_instructions, - send_recv - } = self; + send_recv, + } = self; let mut cpu_progressed = 0; let max_core = cpu.num_core(); let mut index_unit = 0; + let now = SystemTime::now(); while (cpu_progressed > -2) { let mut core_result = InstructionStatus::Completed; - while core_result.is_completed() && let Some(core_instruction) = core_instructions.get_mut(index_unit){ + while core_result.is_completed() + && let Some(core_instruction) = core_instructions.get_mut(index_unit) + { core_result = InstructionStatus::NotExecuted; let CoreInstruction { instructions, @@ -115,14 +145,19 @@ impl<'a> Executable<'a> { *program_counter += 1; } } - if handle_send_recv(cpu, core_instructions, send_recv, core_result) { cpu_progressed = 0; } + if handle_send_recv(cpu, core_instructions, send_recv, core_result) { + cpu_progressed = 0; + } handle_wait_sync(cpu, core_instructions, core_result); index_unit = if index_unit + 1 >= max_core { - cpu_progressed-=1; + cpu_progressed -= 1; 0 } else { index_unit + 1 }; + if (now.elapsed().unwrap() > Duration::from_secs(1)) { + print_status(&core_instructions); + } } } @@ -134,9 +169,9 @@ impl<'a> Executable<'a> { &mut self.cpu } - pub fn dump(&self) { + pub fn dump(&self) { let core_instructions = &self.core_instructions; - for (i, core_instruction) in core_instructions.iter().enumerate() { + for (i, core_instruction) in core_instructions.iter().enumerate() { eprintln!("INST OF CORE {}:", i); for inst in &core_instruction.instructions { inst.dump(); @@ -145,13 +180,12 @@ impl<'a> Executable<'a> { } } -fn handle_wait_sync<'a, 'b, 'c >(cpu: &'b mut CPU<'a>, core_instructions: &'c mut [CoreInstruction], core_result: InstructionStatus) -where 'a : 'b, - 'a : 'c +fn handle_wait_sync<'a, 'b, 'c>( + cpu: &'b mut CPU<'a>, + core_instructions: &'c mut [CoreInstruction], + core_result: InstructionStatus, +) where + 'a: 'b, + 'a: 'c, { } - - - - - diff --git a/backend-simulators/pim/pim-simulator/src/lib/tracing/mod.rs b/backend-simulators/pim/pim-simulator/src/lib/tracing/mod.rs index c918b2c..0821e7a 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/tracing/mod.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/tracing/mod.rs @@ -1,11 +1,10 @@ mod tracing_isa; mod disable; mod pretty_print; - -#[cfg(feature = "tracing")] use std::{fs::File, path::{ PathBuf}}; use std::sync::{LazyLock, Mutex}; + use crate::Executable; #[cfg(feature = "tracing")]