From 91ef6d9bc3eabae0b14dc4c4354a37ac84c8fb88 Mon Sep 17 00:00:00 2001
From: ilgeco <gabriele.magnani@mail.polimi.it>
Date: Wed, 4 Mar 2026 19:56:30 +0100
Subject: [PATCH] pim-simulator dump inst function

---
 .../pim/pim-simulator/src/lib/instruction_set/mod.rs |  4 ++++
 .../pim/pim-simulator/src/lib/pimcore.rs             | 12 +++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs b/backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs
index 0126def..24e59fc 100644
--- a/backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs
+++ b/backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs
@@ -46,6 +46,10 @@ impl Instruction {
             .with_context(|| format!("Error in core: {}", self.data.core_indx() - 1))
             .unwrap()
     }
+
+    pub(crate) fn dump(&self)  {
+        eprintln!("\t{}", functor_to_name(self.functor as usize));
+    }
 }
 
 pub type Instructions = Vec<Instruction>;
diff --git a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs
index 332b869..3231c90 100644
--- a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs
+++ b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs
@@ -1,7 +1,7 @@
 #![allow(unused)]
 
 use crate::{
-    cpu::CPU, instruction_set::{Instruction, InstructionStatus, Instructions}, memory_manager::type_traits::TryToUsize, send_recv::{SendRecv, handle_send_recv}, tracing::TRACER
+    cpu::CPU, instruction_set::{Instruction, InstructionStatus, Instructions, isa::functor_to_name}, memory_manager::type_traits::TryToUsize, send_recv::{SendRecv, handle_send_recv}, tracing::TRACER
 };
 pub mod cpu;
 pub mod instruction_set;
@@ -131,6 +131,16 @@ impl Executable {
     pub fn cpu_mut(&mut self) -> &mut CPU {
         &mut self.cpu
     }
+
+    pub fn dump(&self)  {
+        let core_instructions = &self.core_instructions;
+        for  (i, core_instruction) in  core_instructions.iter().enumerate() {
+            eprintln!("INST OF CORE {}:", i);
+            for inst in &core_instruction.instructions {
+                inst.dump();
+            }
+        }
+    }
 }
 
 fn handle_wait_sync(cpu: &mut CPU, core_instructions: &mut [CoreInstruction], core_result: InstructionStatus) {