add onnx-mlir submodule
add pim simulator
This commit is contained in:
NiccoloN
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use std::path::Path;
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use pimcore::{Executable, cpu::CPU, instruction_set::{InstructionsBuilder, instruction_data::InstructionDataBuilder, isa::*}};
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fn simple_read(path: &Path) -> Vec<f32> {
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if !path.exists() {
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panic!("{:?} not exists", path)
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}
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std::fs::read_to_string(path)
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.unwrap()
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.split(',')
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.map(|s| s.trim().parse::<f32>().unwrap())
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.collect()
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}
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/// mvmul Test
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fn mvmul_f32(err: &str)
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where
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{
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let mut cpu = CPU::new(0);
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cpu.reserve_crossbar(1, 1024 * size_of::<f32>(), 1024);
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let (memory, crossbars) = cpu.host().get_memory_crossbar();
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let matrix = simple_read(Path::new("./tests/B.txt")) ;
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crossbars.get_mut(0).unwrap().execute_store( &matrix).unwrap();
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let vector = simple_read(Path::new("./tests/A.txt"));
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memory.execute_store(0, &vector).unwrap();
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let mut inst_builder = InstructionsBuilder::new();
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let mut idata_build = InstructionDataBuilder::new();
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idata_build.set_core_indx(0).fix_core_indx();
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inst_builder.make_inst(sldi, idata_build.set_rdimm(1, 0).build());
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inst_builder.make_inst(
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sldi,
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idata_build.set_rdimm(3, 1024 * size_of::<f32>() as i32).build(),
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);
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inst_builder.make_inst(
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setbw,
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idata_build
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.set_ibiw_obiw(8 * size_of::<f32>() as i32, 8 * size_of::<f32>() as i32)
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.build(),
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);
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inst_builder.make_inst(
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mvmul,
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idata_build
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.set_rdr1(3, 1)
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.set_mbiw_immrelu_immgroup(8*size_of::<f32>() as i32, 0, 0)
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.build(),
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);
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let core_instruction = vec![inst_builder.build().into()];
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let mut executable = Executable::new(cpu, core_instruction);
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executable.execute();
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assert!(
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executable
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.cpu_mut()
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.host()
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.load::<f32>(1024 * size_of::<f32>(), 1024*size_of::<f32>()).unwrap()[0].iter().zip(
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simple_read(Path::new("./tests/X.txt")) ).all(|(&a,b) : (&f32, f32)| {a-b < 0.001}),
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"Wrong result for {}",
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err
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);
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}
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#[test]
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fn mvmul_big_test() {
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mvmul_f32("mvmul_f32");
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}
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{"adc_count":16,"array_group_map":{"core0":[0,1,2],"core1":[],"core2":[0,1,2],"core3":[],"core4":[0,1,2],"core5":[]},"cell_precision":2,"core_cnt":6,"inputs_addresses":[0],"outputs_addresses":[532],"xbar_array_count":8,"xbar_size":[64,64]}
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[{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"group":0,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":260,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":260,"op":"sldi","rd":0},{"imm":260,"op":"sldi","rd":1},{"group":1,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":260,"op":"sldi","rd":2},{"len":64,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":780,"op":"sldi","rd":0},{"imm":512,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":16},{"imm":520,"op":"sldi","rd":0},{"imm":780,"op":"sldi","rd":1},{"group":2,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":520,"op":"sldi","rd":2},{"len":64,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":0,"op":"sldi","rd":0},{"core":1,"offset":{"offset_select":0,"offset_value":0},"op":"send","rd":0,"size":64}]
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[{"imm":0,"op":"sldi","rd":0},{"core":0,"offset":{"offset_select":0,"offset_value":0},"op":"recv","rd":0,"size":64},{"imm":532,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"st","rd":0,"rs1":1,"size":64}]
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[{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"group":0,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":260,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":260,"op":"sldi","rd":0},{"imm":260,"op":"sldi","rd":1},{"group":1,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":260,"op":"sldi","rd":2},{"len":64,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":780,"op":"sldi","rd":0},{"imm":512,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":16},{"imm":520,"op":"sldi","rd":0},{"imm":780,"op":"sldi","rd":1},{"group":2,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":520,"op":"sldi","rd":2},{"len":64,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":0,"op":"sldi","rd":0},{"core":3,"offset":{"offset_select":0,"offset_value":0},"op":"send","rd":0,"size":64}]
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[{"imm":0,"op":"sldi","rd":0},{"core":2,"offset":{"offset_select":0,"offset_value":0},"op":"recv","rd":0,"size":64},{"imm":596,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"st","rd":0,"rs1":1,"size":64}]
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[{"imm":260,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":0,"op":"sldi","rd":0},{"imm":260,"op":"sldi","rd":1},{"group":0,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":780,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":520,"op":"sldi","rd":0},{"imm":780,"op":"sldi","rd":1},{"group":1,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":520,"op":"sldi","rd":2},{"len":4,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":1040,"op":"sldi","rd":0},{"imm":512,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":16},{"imm":1040,"op":"sldi","rd":0},{"imm":1040,"op":"sldi","rd":1},{"group":2,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":1040,"op":"sldi","rd":2},{"len":4,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":0,"op":"sldi","rd":0},{"core":5,"offset":{"offset_select":0,"offset_value":0},"op":"send","rd":0,"size":4}]
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[{"imm":0,"op":"sldi","rd":0},{"core":4,"offset":{"offset_select":0,"offset_value":0},"op":"recv","rd":0,"size":4},{"imm":660,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"st","rd":0,"rs1":1,"size":4}]
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{"adc_count":16,"array_group_map":{"core0":[0,1,2],"core1":[],"core2":[0,1,2],"core3":[],"core4":[0,1,2],"core5":[]},"cell_precision":2,"core_cnt":6,"inputs_addresses":[0],"outputs_addresses":[528],"xbar_array_count":8,"xbar_size":[64,64]}
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[{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"group":0,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":256,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":256,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"group":1,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":256,"op":"sldi","rd":2},{"len":256,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":768,"op":"sldi","rd":0},{"imm":512,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":16},{"imm":512,"op":"sldi","rd":0},{"imm":768,"op":"sldi","rd":1},{"group":2,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":512,"op":"sldi","rd":2},{"len":256,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":0,"op":"sldi","rd":0},{"core":1,"offset":{"offset_select":0,"offset_value":0},"op":"send","rd":0,"size":256}]
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[{"imm":0,"op":"sldi","rd":0},{"imm":1056,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":256,"op":"sldi","rd":0},{"core":0,"offset":{"offset_select":0,"offset_value":0},"op":"recv","rd":0,"size":256},{"imm":256,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"imm":0,"op":"sldi","rd":2},{"len":256,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":528,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"st","rd":0,"rs1":1,"size":256}]
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[{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"group":0,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":256,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":256,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"group":1,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":256,"op":"sldi","rd":2},{"len":256,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":768,"op":"sldi","rd":0},{"imm":512,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":16},{"imm":512,"op":"sldi","rd":0},{"imm":768,"op":"sldi","rd":1},{"group":2,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":512,"op":"sldi","rd":2},{"len":256,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":0,"op":"sldi","rd":0},{"core":3,"offset":{"offset_select":0,"offset_value":0},"op":"send","rd":0,"size":256}]
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[{"imm":0,"op":"sldi","rd":0},{"imm":1312,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":256,"op":"sldi","rd":0},{"core":2,"offset":{"offset_select":0,"offset_value":0},"op":"recv","rd":0,"size":256},{"imm":256,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"imm":0,"op":"sldi","rd":2},{"len":256,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":784,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"st","rd":0,"rs1":1,"size":256}]
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[{"imm":256,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":0,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"group":0,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":768,"op":"sldi","rd":0},{"imm":256,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":256},{"imm":512,"op":"sldi","rd":0},{"imm":768,"op":"sldi","rd":1},{"group":1,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":512,"op":"sldi","rd":2},{"len":16,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":1024,"op":"sldi","rd":0},{"imm":512,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":16},{"imm":1024,"op":"sldi","rd":0},{"imm":1024,"op":"sldi","rd":1},{"group":2,"mbiw":8,"op":"mvmul","rd":0,"relu":0,"rs1":1},{"imm":0,"op":"sldi","rd":0},{"imm":0,"op":"sldi","rd":1},{"imm":1024,"op":"sldi","rd":2},{"len":16,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":0,"op":"sldi","rd":0},{"core":5,"offset":{"offset_select":0,"offset_value":0},"op":"send","rd":0,"size":16}]
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[{"imm":0,"op":"sldi","rd":0},{"imm":1568,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"ld","rd":0,"rs1":1,"size":16},{"imm":16,"op":"sldi","rd":0},{"core":4,"offset":{"offset_select":0,"offset_value":0},"op":"recv","rd":0,"size":16},{"imm":16,"op":"sldi","rd":0},{"imm":16,"op":"sldi","rd":1},{"imm":0,"op":"sldi","rd":2},{"len":16,"offset":{"offset_select":0,"offset_value":0},"op":"vvadd","rd":0,"rs1":1,"rs2":2},{"imm":1040,"op":"sldi","rd":0},{"imm":16,"op":"sldi","rd":1},{"offset":{"offset_select":0,"offset_value":0},"op":"st","rd":0,"rs1":1,"size":16}]
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use std::{fs, io::BufReader, path::Path};
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use anyhow::{Context, Result};
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use pimcore::json_to_instruction::json_to_executor;
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use serde_json::Value;
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fn collect_json_from_subfolders<P: AsRef<Path>>(root: P) -> Result<Vec<(Value, Vec<Value>)>> {
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let mut result = Vec::new();
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for entry in fs::read_dir(root)? {
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let entry = entry.context("Root not found")?;
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let path = entry.path();
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if path.is_dir() {
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let mut cores = Vec::new();
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let mut config: Option<Value> = None;
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for sub_entry in fs::read_dir(&path)
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.with_context(|| format!("File {} not readable", path.display()))?
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{
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let sub_entry =
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sub_entry.with_context(|| format!("File {} not readable", path.display()))?;
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let sub_path = sub_entry.path();
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if sub_path.is_file()
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&& sub_path.extension().and_then(|s| s.to_str()) == Some("json")
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{
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let file = fs::File::open(&sub_path)
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.with_context(|| format!("Subpath {} not opened", sub_path.display()))?;
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let reader = BufReader::new(file);
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let val: Value = serde_json::from_reader(reader).with_context(|| format!(
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"Serde reader fail for subpath {}",
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sub_path.display()
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))?;
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if sub_path.file_name().unwrap() == "config.json" {
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config = Some(val);
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} else {
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cores.push(val);
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}
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}
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}
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result.push((config.unwrap(), cores));
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}
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}
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Ok(result)
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}
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#[test]
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fn json_folder_tester() {
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let examples = collect_json_from_subfolders("./tests/data").unwrap();
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for example in examples {
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let (config, cores) = example;
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json_to_executor::json_to_executor(config, cores.iter()).execute();
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}
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}
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use pimcore::{Executable, cpu::CPU, instruction_set::{InstructionType, InstructionsBuilder, instruction_data::InstructionDataBuilder, isa::*}};
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#[test]
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#[should_panic(expected = "Function not found for the requested size") ]
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fn wrong_size_place_holder() {
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let cpu = CPU::new(0);
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let mut inst_builder = InstructionsBuilder::new();
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let mut idata_build = InstructionDataBuilder::new();
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idata_build.set_core_indx(0).fix_core_indx();
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inst_builder.make_inst(
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setbw,
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idata_build
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.set_ibiw_obiw(55, 55)
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.build(),
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);
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inst_builder.make_inst(
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vvadd,
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idata_build
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.set_rdr1r2(3, 1, 2)
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.set_imm_len(8 * size_of::<f32>() as i32)
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.build(),
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);
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let core_instruction = vec![inst_builder.build().into()];
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let mut executable = Executable::new(cpu, core_instruction);
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executable.execute();
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||||
}
|
||||
|
||||
|
||||
|
||||
fn place_holder(inst : InstructionType) {
|
||||
let mut cpu = CPU::new(0);
|
||||
let mut idata_build = InstructionDataBuilder::new();
|
||||
idata_build.set_core_indx(0).fix_core_indx();
|
||||
inst(&mut cpu, idata_build.build()).unwrap();
|
||||
}
|
||||
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vvadd_placeholder() {
|
||||
place_holder(vvadd);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vvsub_placeholder() {
|
||||
place_holder(vvsub);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vvmul_placeholder() {
|
||||
place_holder(vvmul);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vvdmul_placeholder() {
|
||||
place_holder(vvdmul);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vvmax_placeholder() {
|
||||
place_holder(vvmax);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vavg_placeholder() {
|
||||
place_holder(vavg);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vrelu_placeholder() {
|
||||
place_holder(vrelu);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vtanh_placeholder() {
|
||||
place_holder(vtanh);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn vsigm_placeholder() {
|
||||
place_holder(vsigm);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic(expected = "You are calling a placeholder, the real call is the generic version") ]
|
||||
fn mvmul_placeholder() {
|
||||
place_holder(mvmul);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic ]
|
||||
fn vvsll_why_inst() {
|
||||
place_holder(vvsll);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic ]
|
||||
fn vvsra_why_inst() {
|
||||
place_holder(vvsra);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,294 @@
|
||||
use pimcore::{
|
||||
Executable, CoreInstructionsBuilder,
|
||||
cpu::CPU,
|
||||
instruction_set::{InstructionsBuilder, instruction_data::InstructionDataBuilder, isa::*},
|
||||
};
|
||||
|
||||
#[test]
|
||||
fn ld_test() {
|
||||
let mut cpu = CPU::new(1);
|
||||
let mut core_instruction_builder = CoreInstructionsBuilder::new(1);
|
||||
let buff: [f32; _] = [
|
||||
1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
|
||||
];
|
||||
cpu.host().execute_store(0, &buff).unwrap();
|
||||
let mut inst_builder = InstructionsBuilder::new();
|
||||
let mut idata_build = InstructionDataBuilder::new();
|
||||
idata_build.set_core_indx(1).fix_core_indx();
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, 0).build());
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(2, 0).build());
|
||||
inst_builder.make_inst(
|
||||
ld,
|
||||
idata_build
|
||||
.set_rdr1(1, 2)
|
||||
.set_imm_len(10 * size_of::<f32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
core_instruction_builder.set_core(1, inst_builder.build());
|
||||
let mut executable = Executable::new(cpu, core_instruction_builder.build());
|
||||
executable.execute();
|
||||
let res = executable
|
||||
.cpu_mut()
|
||||
.core(1)
|
||||
.load::<f32>(0, 10 * size_of::<f32>());
|
||||
|
||||
assert_eq!(
|
||||
res.unwrap()[0],
|
||||
[1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0],
|
||||
"LD failed to load"
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn st_test() {
|
||||
let mut cpu = CPU::new(1);
|
||||
let mut core_instruction_builder = CoreInstructionsBuilder::new(1);
|
||||
let buff: [f32; _] = [
|
||||
1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
|
||||
];
|
||||
cpu.core(1).execute_store(0, &buff).unwrap();
|
||||
let mut inst_builder = InstructionsBuilder::new();
|
||||
let mut idata_build = InstructionDataBuilder::new();
|
||||
idata_build.set_core_indx(1).fix_core_indx();
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, 0).build());
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(2, 0).build());
|
||||
inst_builder.make_inst(
|
||||
st,
|
||||
idata_build
|
||||
.set_rdr1(1, 2)
|
||||
.set_imm_len(10 * size_of::<f32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
core_instruction_builder.set_core(1, inst_builder.build());
|
||||
let mut executable = Executable::new(cpu, core_instruction_builder.build());
|
||||
executable.execute();
|
||||
let res = executable
|
||||
.cpu_mut()
|
||||
.host()
|
||||
.load::<f32>(0, 10 * size_of::<f32>());
|
||||
|
||||
assert_eq!(
|
||||
res.unwrap()[0],
|
||||
[1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0],
|
||||
"ST failed to store"
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn lldi_test() {
|
||||
let cpu = CPU::new(1);
|
||||
let mut core_instruction_builder = CoreInstructionsBuilder::new(1);
|
||||
let mut inst_builder = InstructionsBuilder::new();
|
||||
let mut idata_build = InstructionDataBuilder::new();
|
||||
idata_build.set_core_indx(1).fix_core_indx();
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, 0).build());
|
||||
inst_builder.make_inst(
|
||||
lldi,
|
||||
idata_build
|
||||
.set_rdimm(1, 0xff)
|
||||
.set_imm_len(10 * size_of::<i32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
core_instruction_builder.set_core(1, inst_builder.build());
|
||||
let mut executable = Executable::new(cpu, core_instruction_builder.build());
|
||||
executable.execute();
|
||||
let res = executable
|
||||
.cpu_mut()
|
||||
.core(1)
|
||||
.load::<i32>(0, 10 * size_of::<i32>());
|
||||
|
||||
assert_eq!(
|
||||
res.unwrap()[0],
|
||||
[-1, -1, -1, -1, -1, -1, -1, -1, -1, -1],
|
||||
"Lldi failed to memset"
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn lmv_test() {
|
||||
let mut cpu = CPU::new(1);
|
||||
let mut core_instruction_builder = CoreInstructionsBuilder::new(1);
|
||||
let buff: [f32; _] = [
|
||||
1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
|
||||
];
|
||||
cpu.core(1).execute_store(0, &buff).unwrap();
|
||||
let mut inst_builder = InstructionsBuilder::new();
|
||||
let mut idata_build = InstructionDataBuilder::new();
|
||||
idata_build.set_core_indx(1).fix_core_indx();
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(2, 0).build());
|
||||
inst_builder.make_inst(
|
||||
sldi,
|
||||
idata_build
|
||||
.set_rdimm(1, 8 * size_of::<f32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
inst_builder.make_inst(
|
||||
lmv,
|
||||
idata_build
|
||||
.set_rdr1(1, 2)
|
||||
.set_imm_len(8 * size_of::<f32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
core_instruction_builder.set_core(1, inst_builder.build());
|
||||
let mut executable = Executable::new(cpu, core_instruction_builder.build());
|
||||
executable.execute();
|
||||
let res = executable
|
||||
.cpu_mut()
|
||||
.core(1)
|
||||
.load::<f32>(0, 16 * size_of::<f32>());
|
||||
|
||||
assert_eq!(
|
||||
res.unwrap()[0],
|
||||
[
|
||||
1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0,
|
||||
],
|
||||
"lmv failed to store"
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn simple_send_recv_test() {
|
||||
let mut cpu = CPU::new(2);
|
||||
let mut core_instruction_builder = CoreInstructionsBuilder::new(2);
|
||||
let buff: [f32; _] = [
|
||||
1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
|
||||
];
|
||||
cpu.core(1).execute_store(0, &buff).unwrap();
|
||||
let mut inst_builder = InstructionsBuilder::new();
|
||||
let mut idata_build = InstructionDataBuilder::new();
|
||||
idata_build.set_core_indx(1).fix_core_indx();
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, 3*size_of::<f32>() as i32).build());
|
||||
inst_builder.make_inst(
|
||||
send,
|
||||
idata_build
|
||||
.set_r1(1)
|
||||
.set_imm_core(2)
|
||||
.set_imm_len(8 * size_of::<f32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
core_instruction_builder.set_core(1, inst_builder.build());
|
||||
idata_build.set_core_indx(2).fix_core_indx();
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, 0).build());
|
||||
inst_builder.make_inst(
|
||||
recv,
|
||||
idata_build
|
||||
.set_rd(1)
|
||||
.set_imm_core(1)
|
||||
.set_imm_len(8 * size_of::<f32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
core_instruction_builder.set_core(2, inst_builder.build());
|
||||
let mut executable = Executable::new(cpu, core_instruction_builder.build());
|
||||
executable.execute();
|
||||
let res = executable
|
||||
.cpu_mut()
|
||||
.core(2)
|
||||
.load::<f32>(0, 8 * size_of::<f32>());
|
||||
|
||||
assert_eq!(
|
||||
res.unwrap()[0],
|
||||
[
|
||||
4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0
|
||||
],
|
||||
"send_recv failed to store"
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
|
||||
// 1 -> 3
|
||||
// 2 -> 3
|
||||
// 3 <- 2
|
||||
// 4 -> 2
|
||||
// 3 <- 4
|
||||
// 2 <- 4
|
||||
// 4 -> 3
|
||||
// 3 <- 1
|
||||
|
||||
#[test]
|
||||
fn multiple_send_recv_test() {
|
||||
let mut cpu = CPU::new(4);
|
||||
let mut core_instruction_builder = CoreInstructionsBuilder::new(4);
|
||||
let buff: [f32; _] = [
|
||||
1.0, 1.0, 1.0, 1.0, 1.0
|
||||
];
|
||||
cpu.core(1).execute_store(0, &buff).unwrap();
|
||||
let buff: [f32; _] = [
|
||||
2.0, 2.0, 2.0, 2.0, 2.0
|
||||
];
|
||||
cpu.core(2).execute_store(0, &buff).unwrap();
|
||||
let buff: [f32; _] = [
|
||||
3.0, 3.0, 3.0, 3.0, 3.0
|
||||
];
|
||||
cpu.core(3).execute_store(0, &buff).unwrap();
|
||||
let buff: [f32; _] = [
|
||||
4.0, 4.0, 4.0, 4.0, 4.0
|
||||
];
|
||||
cpu.core(4).execute_store(0, &buff).unwrap();
|
||||
|
||||
let send_inst = |cpu :&mut CPU, core_instruction_builder: &mut CoreInstructionsBuilder, inst_builder: &mut InstructionsBuilder, from : i32, to : i32| {
|
||||
let mut idata_build = InstructionDataBuilder::new();
|
||||
idata_build.set_core_indx(from).fix_core_indx();
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, from*size_of::<f32>() as i32).build());
|
||||
inst_builder.make_inst(
|
||||
send,
|
||||
idata_build
|
||||
.set_r1(1)
|
||||
.set_imm_core(to)
|
||||
.set_imm_len(size_of::<f32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
};
|
||||
|
||||
let recv_inst = |cpu :&mut CPU, core_instruction_builder: &mut CoreInstructionsBuilder, mut inst_builder: &mut InstructionsBuilder, to : i32, from : i32| {
|
||||
let mut idata_build = InstructionDataBuilder::new();
|
||||
idata_build.set_core_indx(to).fix_core_indx();
|
||||
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, from*size_of::<f32>() as i32).build());
|
||||
inst_builder.make_inst(
|
||||
recv,
|
||||
idata_build
|
||||
.set_rd(1)
|
||||
.set_imm_core(from)
|
||||
.set_imm_len(size_of::<f32>() as i32)
|
||||
.build(),
|
||||
);
|
||||
};
|
||||
let mut inst_builder = InstructionsBuilder::new();
|
||||
|
||||
|
||||
// 1 -> 3
|
||||
send_inst(&mut cpu,&mut core_instruction_builder,&mut inst_builder,1, 3);
|
||||
core_instruction_builder.set_core(1, inst_builder.build());
|
||||
|
||||
// 2 -> 3
|
||||
// 2 <- 4
|
||||
send_inst(&mut cpu,&mut core_instruction_builder,&mut inst_builder,2, 3);
|
||||
recv_inst(&mut cpu,&mut core_instruction_builder,&mut inst_builder,2, 4);
|
||||
core_instruction_builder.set_core(2, inst_builder.build());
|
||||
|
||||
// 3 <- 2
|
||||
// 3 <- 4
|
||||
// 3 <- 1
|
||||
recv_inst(&mut cpu,&mut core_instruction_builder,&mut inst_builder,3, 2);
|
||||
recv_inst(&mut cpu,&mut core_instruction_builder,&mut inst_builder,3, 4);
|
||||
recv_inst(&mut cpu,&mut core_instruction_builder,&mut inst_builder,3, 1);
|
||||
core_instruction_builder.set_core(3, inst_builder.build());
|
||||
// 4 -> 2
|
||||
// 4 -> 3
|
||||
send_inst(&mut cpu,&mut core_instruction_builder,&mut inst_builder,4, 2);
|
||||
send_inst(&mut cpu,&mut core_instruction_builder,&mut inst_builder,4, 3);
|
||||
core_instruction_builder.set_core(4, inst_builder.build());
|
||||
|
||||
let mut executable = Executable::new(cpu, core_instruction_builder.build());
|
||||
executable.execute();
|
||||
let res = executable
|
||||
.cpu_mut()
|
||||
.core(3)
|
||||
.load::<f32>(4, 4 * size_of::<f32>());
|
||||
|
||||
assert_eq!(
|
||||
res.unwrap()[0],
|
||||
[ 1.0, 2.0, 3.0, 4.0 ],
|
||||
"send_recv failed to store"
|
||||
);
|
||||
}
|
||||
Reference in New Issue
Block a user