nnicolosi/Raptor
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

implement vmv in pim-simulator
Validate Operations / validate-operations (push) Has been cancelled
Details

Browse Source 
fix offset selection implementation to match the pim isa
automatic code format for pim-simulator
This commit is contained in:
NiccoloN
2026-07-31 17:24:19 +02:00
parent a0131c6f7a
commit 9ca1a0ed9f
23 changed files with 584 additions and 497 deletions
Download Patch File Download Diff File Expand all files Collapse all files
backend-simulators/pim/pim-simulator/tests/sync.rs
+45 -43
View File
@@ -1,7 +1,7 @@
mod common;
use pimcore::{
Executable, CoreInstructionsBuilder,
CoreInstructionsBuilder, Executable,
instruction_set::{InstructionsBuilder, instruction_data::InstructionDataBuilder, isa::*},
};
@@ -158,7 +158,12 @@ fn simple_send_recv_test() {
let mut inst_builder = InstructionsBuilder::new();
let mut idata_build = InstructionDataBuilder::new();
idata_build.set_core_indx(1).fix_core_indx();
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, 3*size_of::<f32>() as i32).build());
inst_builder.make_inst(
sldi,
idata_build
.set_rdimm(1, 3 * size_of::<f32>() as i32)
.build(),
);
inst_builder.make_inst(
send,
idata_build
@@ -188,15 +193,11 @@ fn simple_send_recv_test() {
assert_eq!(
res.unwrap()[0],
[
4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0
],
[4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0],
"send_recv failed to store"
);
}
// 1 -> 3
// 2 -> 3
// 3 <- 2
@@ -210,53 +211,54 @@ fn simple_send_recv_test() {
fn multiple_send_recv_test() {
let mut cpu = common::empty_cpu(4);
let mut core_instruction_builder = CoreInstructionsBuilder::new(4);
let buff: [f32; _] = [
1.0, 1.0, 1.0, 1.0, 1.0
];
let buff: [f32; _] = [1.0, 1.0, 1.0, 1.0, 1.0];
cpu.core(1).execute_store(0, &buff).unwrap();
let buff: [f32; _] = [
2.0, 2.0, 2.0, 2.0, 2.0
];
let buff: [f32; _] = [2.0, 2.0, 2.0, 2.0, 2.0];
cpu.core(2).execute_store(0, &buff).unwrap();
let buff: [f32; _] = [
3.0, 3.0, 3.0, 3.0, 3.0
];
let buff: [f32; _] = [3.0, 3.0, 3.0, 3.0, 3.0];
cpu.core(3).execute_store(0, &buff).unwrap();
let buff: [f32; _] = [
4.0, 4.0, 4.0, 4.0, 4.0
];
let buff: [f32; _] = [4.0, 4.0, 4.0, 4.0, 4.0];
cpu.core(4).execute_store(0, &buff).unwrap();
let send_inst = |inst_builder: &mut InstructionsBuilder, from: i32, to: i32| {
let mut idata_build = InstructionDataBuilder::new();
idata_build.set_core_indx(from).fix_core_indx();
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, from*size_of::<f32>() as i32).build());
inst_builder.make_inst(
send,
idata_build
.set_r1(1)
.set_imm_core(to)
.set_imm_len(size_of::<f32>() as i32)
.build(),
);
let mut idata_build = InstructionDataBuilder::new();
idata_build.set_core_indx(from).fix_core_indx();
inst_builder.make_inst(
sldi,
idata_build
.set_rdimm(1, from * size_of::<f32>() as i32)
.build(),
);
inst_builder.make_inst(
send,
idata_build
.set_r1(1)
.set_imm_core(to)
.set_imm_len(size_of::<f32>() as i32)
.build(),
);
};
let recv_inst = |inst_builder: &mut InstructionsBuilder, to: i32, from: i32| {
let mut idata_build = InstructionDataBuilder::new();
idata_build.set_core_indx(to).fix_core_indx();
inst_builder.make_inst(sldi, idata_build.set_rdimm(1, from*size_of::<f32>() as i32).build());
inst_builder.make_inst(
recv,
idata_build
.set_rd(1)
.set_imm_core(from)
.set_imm_len(size_of::<f32>() as i32)
.build(),
);
let mut idata_build = InstructionDataBuilder::new();
idata_build.set_core_indx(to).fix_core_indx();
inst_builder.make_inst(
sldi,
idata_build
.set_rdimm(1, from * size_of::<f32>() as i32)
.build(),
);
inst_builder.make_inst(
recv,
idata_build
.set_rd(1)
.set_imm_core(from)
.set_imm_len(size_of::<f32>() as i32)
.build(),
);
};
let mut inst_builder = InstructionsBuilder::new();
// 1 -> 3
send_inst(&mut inst_builder, 1, 3);
core_instruction_builder.set_core(1, inst_builder.build());
@@ -289,7 +291,7 @@ fn multiple_send_recv_test() {
assert_eq!(
res.unwrap()[0],
[ 1.0, 2.0, 3.0, 4.0 ],
[1.0, 2.0, 3.0, 4.0],
"send_recv failed to store"
);
}