From ad56888b0bd5cb88a27c15a1fdfb43b477d56881 Mon Sep 17 00:00:00 2001 From: ilgeco Date: Wed, 13 May 2026 13:32:09 +0200 Subject: [PATCH 1/3] Broken pim-sim commit --- .../pim/pim-simulator/Cargo.toml | 1 + .../src/bin/pim-simulator/main.rs | 39 +++++++------- .../src/lib/instruction_set/isa.rs | 13 ++++- .../src/lib/instruction_set/mod.rs | 2 +- .../json_to_instruction/json_to_executor.rs | 32 ++++++------ .../pim/pim-simulator/src/lib/pimcore.rs | 52 +++++++++++++++++-- 6 files changed, 97 insertions(+), 42 deletions(-) diff --git a/backend-simulators/pim/pim-simulator/Cargo.toml b/backend-simulators/pim/pim-simulator/Cargo.toml index 425bb31..ff51ef6 100644 --- a/backend-simulators/pim/pim-simulator/Cargo.toml +++ b/backend-simulators/pim/pim-simulator/Cargo.toml @@ -34,3 +34,4 @@ plotly = {version="0.8", optional=true} rayon = "1.12.0" faer = "0.24.0" faer-traits = "0.24.0" +mimalloc = "0.1.50" diff --git a/backend-simulators/pim/pim-simulator/src/bin/pim-simulator/main.rs b/backend-simulators/pim/pim-simulator/src/bin/pim-simulator/main.rs index 77ea143..4411a54 100644 --- a/backend-simulators/pim/pim-simulator/src/bin/pim-simulator/main.rs +++ b/backend-simulators/pim/pim-simulator/src/bin/pim-simulator/main.rs @@ -1,3 +1,8 @@ +use mimalloc::MiMalloc; + +#[global_allocator] +static GLOBAL: MiMalloc = MiMalloc; + use anyhow::{Context, Result, bail}; use clap::Parser; use glob::glob; @@ -7,8 +12,8 @@ use pimcore::memory_manager::CoreMemory; use pimcore::tracing::TRACER; use serde_json::Value; use std::collections::HashMap; -use std::fs::{self, read_link}; -use std::io::Write; +use std::fs::{self, File, read_link}; +use std::io::{ BufReader, Write}; use std::path::PathBuf; /// Program to simulate core execution configuration @@ -44,12 +49,12 @@ fn main() -> Result<()> { let args = Args::parse(); let config_json = retrive_config(&args)?; - let core_jsons = retrive_cores(&args)?; + let core_jsons = retrive_cores_file(&args)?; let memory = retrive_memory(&args)?; let global_crossbars = get_crossbars(&config_json, &args).unwrap(); let crossbars = map_crossbars_to_cores(&config_json, &args, &global_crossbars); let mut executor = - json_to_executor::json_to_executor(config_json, core_jsons.iter(), crossbars); + json_to_executor::json_to_executor(config_json, core_jsons, crossbars); set_memory(&mut executor, memory); TRACER .lock() @@ -140,8 +145,7 @@ fn get_crossbars(config: &Value, args: &Args) -> anyhow::Result Result> { Ok(memory_vector) } -fn retrive_cores(args: &Args) -> Result, anyhow::Error> { - let mut core_jsons: Vec = Vec::new(); +fn retrive_cores_file(args: &Args) -> Result>, anyhow::Error> { + let mut core_file_reader: Vec> = Vec::new(); if let Some(cores_override) = &args.cores { for core in cores_override { - let content = fs::read_to_string(core) - .with_context(|| format!("Failed to read core file: {:?}", cores_override))?; - let json: Value = - serde_json::from_str(&content).context("Failed to parse core json override")?; - core_jsons.push(json); + let file = File::open(core)?; + let reader = BufReader::new(file); + core_file_reader.push(reader); } } else if let Some(folder) = args.folder.as_ref() { let pattern = folder.join("core*.json"); @@ -242,17 +244,14 @@ fn retrive_cores(args: &Args) -> Result, anyhow::Error> { bail!("No core*.json files found in {:?}", folder); } for entry in paths { - let path = entry; - let content = fs::read_to_string(&path) - .with_context(|| format!("Failed to read core file: {:?}", path))?; - let json: Value = serde_json::from_str(&content) - .with_context(|| format!("Failed to parse JSON in {:?}", path))?; - core_jsons.push(json); + let file = File::open(entry)?; + let reader = BufReader::new(file); + core_file_reader.push(reader); } } else { bail!("Either --core or --folder must be provided to find core definitions."); } - Ok(core_jsons) + Ok(core_file_reader) } fn retrive_config(args: &Args) -> Result { diff --git a/backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs b/backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs index 28f1269..25a078e 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs @@ -16,7 +16,7 @@ use anyhow::{Context, Result, ensure}; use rayon::prelude::*; use paste::paste; -use std::{borrow::Cow, cell::OnceCell, collections::HashMap}; +use std::{borrow::Cow, cell::OnceCell, collections::HashMap }; use std::{collections::HashSet, sync::LazyLock}; macro_rules! add_name { @@ -35,7 +35,7 @@ macro_rules! add_name_simd { }; } -static NAMES: LazyLock> = LazyLock::new(|| { +pub static NAMES: LazyLock> = LazyLock::new(|| { let mut hash = HashMap::new(); add_name!(hash, sldi); add_name!(hash, sld); @@ -775,10 +775,19 @@ pub fn lmv(cores: &mut CPU, data: InstructionData) -> Result Ok(InstructionStatus::Completed) } +pub fn isa_send(functor : usize) -> bool{ + (send as *const () as usize) == functor +} + pub fn send(cores: &mut CPU, data: InstructionData) -> Result { Ok(InstructionStatus::Sending(data)) } +pub fn isa_recv(functor : usize) -> bool{ + println!("{} {} ", functor, (recv as *const () as usize)); + (recv as *const () as usize) == functor +} + pub fn recv(cores: &mut CPU, data: InstructionData) -> Result { Ok(InstructionStatus::Reciving(data)) } diff --git a/backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs b/backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs index af6da35..81cf77a 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs @@ -14,7 +14,7 @@ pub mod helper; #[derive(Clone, Copy, Debug)] pub struct Instruction { pub data: InstructionData, - functor: InstructionType, + pub functor: InstructionType, } #[derive(Debug, Clone, Copy, Default)] diff --git a/backend-simulators/pim/pim-simulator/src/lib/json_to_instruction/json_to_executor.rs b/backend-simulators/pim/pim-simulator/src/lib/json_to_instruction/json_to_executor.rs index 45fdc2c..12fbd7b 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/json_to_instruction/json_to_executor.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/json_to_instruction/json_to_executor.rs @@ -1,11 +1,15 @@ use core::panic; -use std::collections::HashMap; +use std::io::{Read, Write}; +use std::{collections::HashMap, fs::File, io::BufReader}; -use serde_json::{Map, Value}; +use serde_json::{Deserializer, Map, Value}; use crate::{ CoreInstructionsBuilder, Executable, - cpu::{CPU, crossbar::{self, Crossbar}}, + cpu::{ + CPU, + crossbar::{self, Crossbar}, + }, instruction_set::{ InstructionsBuilder, instruction_data::{self, InstructionData, InstructionDataBuilder}, @@ -14,11 +18,10 @@ use crate::{ memory_manager::type_traits::TryToUsize, }; - pub fn json_to_executor<'a, 'b>( config: Value, - mut cores: impl Iterator, - crossbars : Vec> + mut cores: Vec>, + crossbars: Vec>, ) -> Executable<'a> { let cell_precision = config.get("cell_precision").unwrap().as_i64().unwrap() as i32; let core_cnt = config.get("core_cnt").unwrap().as_i64().unwrap() as i32 - 1; @@ -29,19 +32,18 @@ pub fn json_to_executor<'a, 'b>( let mut cpu = CPU::new(core_cnt, crossbars); let mut core_insts_builder = CoreInstructionsBuilder::new(core_cnt as usize); - cores.next(); + // Note: cores[0] is intentionally empty and discarded for core_indx in 1..=core_cnt { let mut insts_builder = InstructionsBuilder::new(); let mut inst_data_builder = InstructionDataBuilder::new(); inst_data_builder.set_core_indx(core_indx).fix_core_indx(); - let json_core = cores - .next() - .unwrap_or_else(|| panic!("cores files less than {}", core_indx )); - let json_core_insts = json_core - .as_array() - .unwrap_or_else(|| panic!("core{} has not a list of instruction", core_indx)); - for json_inst in json_core_insts { - json_isa::json_to_instruction(&mut insts_builder, &mut inst_data_builder, json_inst); + let stream = Deserializer::from_reader(&mut cores[core_indx as usize]).into_iter::(); + + for (i, json_inst_result) in stream.enumerate() { + let json_inst = json_inst_result.expect("Failed to parse instruction"); + // Pass the single Value to your parser + json_isa::json_to_instruction(&mut insts_builder, &mut inst_data_builder, &json_inst); + drop(json_inst); } core_insts_builder.set_core(core_indx, insts_builder.build()); } diff --git a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs index 129c8c2..6415092 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs @@ -4,7 +4,10 @@ use std::time::{Duration, SystemTime}; use crate::{ cpu::CPU, - instruction_set::{Instruction, InstructionStatus, Instructions, isa::functor_to_name}, + instruction_set::{ + Instruction, InstructionStatus, Instructions, + isa::{NAMES, functor_to_name, isa_recv, isa_send}, + }, memory_manager::type_traits::TryToUsize, send_recv::{SendRecv, handle_send_recv}, tracing::TRACER, @@ -144,8 +147,9 @@ impl<'a> Executable<'a> { cpu_progressed = 0; *program_counter += 1; } - if (now.elapsed().unwrap() > Duration::from_secs(1)) { - print_status(&cores_instructions); + if (now.elapsed().unwrap() > Duration::from_secs(5)) { + print_status(cores_instructions); + check_cycle(cpu, cores_instructions, send_recv); now = SystemTime::now(); } } @@ -170,7 +174,7 @@ impl<'a> Executable<'a> { } print_status(cores_instructions); - #[cfg(feature = "profile_time")] + #[cfg(feature = "profile_time")] TRACER.lock().unwrap().report(); } @@ -193,6 +197,46 @@ impl<'a> Executable<'a> { } } +fn check_cycle(cpu: &mut CPU, cores_instructions: &[CoreInstructions], send_recv: &mut SendRecv) { + //println!("PRINTAAA"); + //*PRINTAAA.lock().unwrap() = true; + //(inst.functor)(cpu, inst.data); + //*PRINTAAA.lock().unwrap() = false; + // + + println!("NAMES"); + for (a,n) in NAMES.iter(){ + println!("{} {}", a, n); + } + + let mut i = 0; + for CoreInstructions { + instructions, + program_counter, + } in cores_instructions + { + if *program_counter >= instructions.len() { + continue; + } + let Instruction { data, functor } = instructions[*program_counter]; + let functor_address = functor as usize; + + print!("Core {} ", i); + i += 1; + match (isa_recv(functor_address), isa_send(functor_address)) { + (true, false) => { + let (receiver, sender) = data.get_core_immcore(); + println!("{} <- {}", receiver, sender); + } + (false, true) => { + let (sender, receiver) = data.get_core_immcore(); + println!("{} -> {}", receiver, sender); + } + _ => {} + } + } +} + fn handle_wait_sync<'a, 'b, 'c>( cpu: &'b mut CPU<'a>, core_instructions: &'c mut [CoreInstructions], From 88bb223bb1caf70b52217dbca225b25dfedd2727 Mon Sep 17 00:00:00 2001 From: ilgeco Date: Wed, 13 May 2026 14:15:41 +0200 Subject: [PATCH 2/3] Fix multiple address bug --- .../pim/pim-simulator/Cargo.toml | 1 - .../src/lib/instruction_set/isa.rs | 46 ++++++++++++++++++- .../pim/pim-simulator/src/lib/pimcore.rs | 12 ----- 3 files changed, 45 insertions(+), 14 deletions(-) diff --git a/backend-simulators/pim/pim-simulator/Cargo.toml b/backend-simulators/pim/pim-simulator/Cargo.toml index ff51ef6..7e8df3a 100644 --- a/backend-simulators/pim/pim-simulator/Cargo.toml +++ b/backend-simulators/pim/pim-simulator/Cargo.toml @@ -1,4 +1,3 @@ - [package] name = "pim-simulator" version = "0.1.0" diff --git a/backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs b/backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs index 25a078e..ca84b9a 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs @@ -81,6 +81,7 @@ pub fn functor_to_name(functor: usize) -> &'static str { /////////////////////////////////////////////////////////////// /////////////////Scalar/register Instructions////////////////// /////////////////////////////////////////////////////////////// +#[inline(never)] pub fn sldi(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_sldi(cores, data); let (core_indx, rd, imm) = data.get_core_rd_imm(); @@ -90,6 +91,7 @@ pub fn sldi(cores: &mut CPU, data: InstructionData) -> Result Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn sld(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_sld(cores, data); let (core_indx, rd, r1) = data.get_core_rd_r1(); @@ -104,6 +106,7 @@ pub fn sld(cores: &mut CPU, data: InstructionData) -> Result Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn sadd(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_sadd(cores, data); let (core_indx, rd, r1, r2) = data.get_core_rd_r1_r2(); @@ -114,6 +117,7 @@ pub fn sadd(cores: &mut CPU, data: InstructionData) -> Result Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn ssub(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_ssub(cores, data); let (core_indx, rd, r1, r2) = data.get_core_rd_r1_r2(); @@ -124,6 +128,7 @@ pub fn ssub(cores: &mut CPU, data: InstructionData) -> Result Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn smul(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_smul(cores, data); let (core_indx, rd, r1, r2) = data.get_core_rd_r1_r2(); @@ -134,6 +139,7 @@ pub fn smul(cores: &mut CPU, data: InstructionData) -> Result Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn saddi(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_saddi(cores, data); let (core_indx, rd, r1, imm) = data.get_core_rd_r1_imm(); @@ -143,6 +149,7 @@ pub fn saddi(cores: &mut CPU, data: InstructionData) -> Result Result { TRACER.lock().unwrap().pre_smuli(cores, data); let (core_indx, rd, r1, imm) = data.get_core_rd_r1_imm(); @@ -217,14 +224,17 @@ pub fn is_setbw(functor: InstructionType) -> bool { functor as usize == setbw as *const () as usize } +#[inline(never)] pub fn setbw(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, this instruction is resolved in the construction phase"); } +#[inline(never)] pub fn mvmul(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn mvm_impl_internal( cores: &mut CPU, data: InstructionData, @@ -309,6 +319,7 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub(super) fn mvmul_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice + UpcastSlice + UpcastSlice, @@ -329,10 +340,12 @@ where } } +#[inline(never)] pub fn vvadd(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vvadd_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -371,10 +384,12 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vvsub(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vvsub_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -416,6 +431,7 @@ pub fn vvmul(cores: &mut CPU, data: InstructionData) -> Result(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -452,10 +468,12 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vvdmul(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vvdmul_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -488,10 +506,12 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vvmax(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vvmax_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -525,22 +545,26 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vvsll(cores: &mut CPU, data: InstructionData) -> Result { panic!( "Shift left on floating point what does it means? who has generated this instruction???" ); } +#[inline(never)] pub fn vvsra(cores: &mut CPU, data: InstructionData) -> Result { panic!( "Shift right on floating point what does it means? who has generated this instruction???" ); } +#[inline(never)] pub fn vavg(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vavg_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -570,10 +594,12 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vrelu(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vrelu_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -600,10 +626,12 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vtanh(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vtanh_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -628,10 +656,12 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vsigm(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vsigm_impl(cores: &mut CPU, data: InstructionData) -> Result where [F]: UpcastSlice, @@ -654,10 +684,12 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vsoftmax(cores: &mut CPU, data: InstructionData) -> Result { panic!("You are calling a placeholder, the real call is the generic version"); } +#[inline(never)] pub(super) fn vsoftmax_impl( cores: &mut CPU, data: InstructionData, @@ -696,14 +728,17 @@ where Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn vmv(cores: &mut CPU, data: InstructionData) -> Result { todo!() } +#[inline(never)] pub fn vrsu(cores: &mut CPU, data: InstructionData) -> Result { todo!() } +#[inline(never)] pub fn vrsl(cores: &mut CPU, data: InstructionData) -> Result { todo!() } @@ -711,6 +746,7 @@ pub fn vrsl(cores: &mut CPU, data: InstructionData) -> Result /////////////////////////////////////////////////////////////// ///Communication/synchronization Instructions///////////////// /////////////////////////////////////////////////////////////// +#[inline(never)] pub fn ld(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_ld(cores, data); let (core, rd, r1, _, imm_len, offset_select, offset_value) = @@ -727,6 +763,7 @@ pub fn ld(cores: &mut CPU, data: InstructionData) -> Result { Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn st(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_st(cores, data); let (core, rd, r1, _, imm_len, offset_select, offset_value) = @@ -743,6 +780,7 @@ pub fn st(cores: &mut CPU, data: InstructionData) -> Result { Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn lldi(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_lldi(cores, data); let (core, rd, imm) = data.get_core_rd_imm(); @@ -759,6 +797,7 @@ pub fn lldi(cores: &mut CPU, data: InstructionData) -> Result Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn lmv(cores: &mut CPU, data: InstructionData) -> Result { TRACER.lock().unwrap().pre_lmv(cores, data); let (core, rd, r1, _, imm_len, offset_select, offset_value) = @@ -775,27 +814,32 @@ pub fn lmv(cores: &mut CPU, data: InstructionData) -> Result Ok(InstructionStatus::Completed) } +#[inline(never)] pub fn isa_send(functor : usize) -> bool{ (send as *const () as usize) == functor } +#[inline(never)] pub fn send(cores: &mut CPU, data: InstructionData) -> Result { Ok(InstructionStatus::Sending(data)) } +#[inline(never)] pub fn isa_recv(functor : usize) -> bool{ - println!("{} {} ", functor, (recv as *const () as usize)); (recv as *const () as usize) == functor } +#[inline(never)] pub fn recv(cores: &mut CPU, data: InstructionData) -> Result { Ok(InstructionStatus::Reciving(data)) } +#[inline(never)] pub fn wait(cores: &mut CPU, data: InstructionData) -> Result { Ok(InstructionStatus::Waiting(data)) } +#[inline(never)] pub fn sync(cores: &mut CPU, data: InstructionData) -> Result { Ok(InstructionStatus::Sync(data)) } diff --git a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs index 6415092..d63c8c8 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs @@ -198,17 +198,6 @@ impl<'a> Executable<'a> { } fn check_cycle(cpu: &mut CPU, cores_instructions: &[CoreInstructions], send_recv: &mut SendRecv) { - //println!("PRINTAAA"); - //*PRINTAAA.lock().unwrap() = true; - //(inst.functor)(cpu, inst.data); - //*PRINTAAA.lock().unwrap() = false; - // - - println!("NAMES"); - for (a,n) in NAMES.iter(){ - println!("{} {}", a, n); - } - let mut i = 0; for CoreInstructions { instructions, @@ -221,7 +210,6 @@ fn check_cycle(cpu: &mut CPU, cores_instructions: &[CoreInstructions], send_recv let Instruction { data, functor } = instructions[*program_counter]; let functor_address = functor as usize; - print!("Core {} ", i); i += 1; match (isa_recv(functor_address), isa_send(functor_address)) { (true, false) => { From c15aba5d9641e1a905fd04326b61e373c0907ed8 Mon Sep 17 00:00:00 2001 From: ilgeco Date: Wed, 13 May 2026 15:05:17 +0200 Subject: [PATCH 3/3] pim-simulator removed useless comment --- .../pim/pim-simulator/src/lib/pimcore.rs | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs index e3ca045..89a9866 100644 --- a/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs +++ b/backend-simulators/pim/pim-simulator/src/lib/pimcore.rs @@ -206,24 +206,20 @@ fn check_cycle(cpu: &mut CPU, cores_instructions: &[CoreInstructions], send_recv enum CoreState { SendingTo(i32), ReceivingFrom(i32), - Working, // Doing math, etc. Not blocked. + Working, Halted, } - // 1. Snapshot the current state of every core let mut states = HashMap::new(); for core_inst in cores_instructions.iter() { if core_inst.program_counter >= core_inst.instructions.len() { - // Assuming we can derive core ID here. If `cores_instructions` doesn't - // give you the core ID easily, you might need to enumerate the loop. continue; } let Instruction { data, functor } = core_inst.instructions[core_inst.program_counter]; let functor_address = functor as usize; - // get_core_immcore() always seems to return (this_core, target_core) let (this_core, target_core) = data.get_core_immcore(); if isa_recv(functor_address) { @@ -231,38 +227,31 @@ fn check_cycle(cpu: &mut CPU, cores_instructions: &[CoreInstructions], send_recv } else if isa_send(functor_address) { states.insert(this_core, CoreState::SendingTo(target_core)); } else { - // Doing other stuff (add, sub, etc). It is NOT blocked. states.insert(this_core, CoreState::Working); } } - // 2. Build the Wait-For Graph let mut wait_for = HashMap::new(); for (&core_id, state) in states.iter() { match state { CoreState::SendingTo(target_core) => { let target_state = states.get(target_core).unwrap_or(&CoreState::Halted); - // We are blocked UNLESS the target is actively receiving from us right now if target_state != &CoreState::ReceivingFrom(core_id) { wait_for.insert(core_id, *target_core); } } CoreState::ReceivingFrom(target_core) => { let target_state = states.get(target_core).unwrap_or(&CoreState::Halted); - // We are blocked UNLESS the target is actively sending to us right now if target_state != &CoreState::SendingTo(core_id) { wait_for.insert(core_id, *target_core); } } CoreState::Working | CoreState::Halted => { - // A working core is not waiting for anyone. - // It has no outgoing edges, which naturally prevents false cycles! } } } - // 3. Detect Cycles strictly among blocked cores let mut visited = HashSet::new(); for &start_core in wait_for.keys() {