This commit is contained in:
@@ -2,8 +2,12 @@
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#define SPATIAL_DIALECT_H
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include "mlir/IR/OpBase.td"
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include "mlir/IR/OpAsmInterface.td"
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include "mlir/IR/BuiltinTypes.td"
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include "mlir/IR/AttrTypeBase.td"
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include "mlir/IR/RegionKindInterface.td"
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include "mlir/Interfaces/ParallelCombiningOpInterface.td"
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include "mlir/Interfaces/SideEffectInterfaces.td"
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def SpatialDialect : Dialect {
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let name = "spat";
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@@ -22,7 +26,9 @@ def SpatTensor :
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// Execution
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//===----------------------------------------------------------------------===//
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def SpatCompute : SpatOp<"compute", [SingleBlock, AttrSizedOperandSegments]> {
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def SpatCompute : SpatOp<"compute",
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[SingleBlock, AttrSizedOperandSegments,
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DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmBlockArgumentNames"]>]> {
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let summary = "Compute region with attached constant weights";
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let arguments = (ins
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@@ -36,14 +42,20 @@ def SpatCompute : SpatOp<"compute", [SingleBlock, AttrSizedOperandSegments]> {
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let regions = (region SizedRegion<1>:$body);
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let extraClassDeclaration = [{
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::mlir::BlockArgument getWeightArgument(unsigned idx);
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::mlir::BlockArgument getInputArgument(unsigned idx);
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}];
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let hasVerifier = 1;
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let hasFolder = 1;
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let hasCustomAssemblyFormat = 1;
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}
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def SpatComputeBatch : SpatOp<"compute_batch",
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[SingleBlock, AttrSizedOperandSegments]> {
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let summary = "Compressed batch of independent equivalent compute lanes";
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[SingleBlock, AttrSizedOperandSegments,
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DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmBlockArgumentNames"]>]> {
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let summary = "Tensor-native batch of equivalent compute lanes with shared weights and packed inputs";
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let arguments = (ins
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I32Attr:$laneCount,
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@@ -57,10 +69,41 @@ def SpatComputeBatch : SpatOp<"compute_batch",
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let regions = (region SizedRegion<1>:$body);
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let extraClassDeclaration = [{
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::mlir::BlockArgument getLaneArgument();
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::mlir::BlockArgument getWeightArgument(unsigned idx);
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::mlir::BlockArgument getInputArgument(unsigned idx);
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::mlir::BlockArgument getOutputArgument(unsigned idx);
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}];
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let hasVerifier = 1;
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let hasCustomAssemblyFormat = 1;
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}
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def SpatInParallelOp : SpatOp<"in_parallel", [
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Pure,
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Terminator,
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DeclareOpInterfaceMethods<InParallelOpInterface>,
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HasParent<"SpatComputeBatch">,
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] # GraphRegionNoTerminator.traits> {
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let summary = "Parallel combining terminator for resultful spat.compute_batch";
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let regions = (region SizedRegion<1>:$region);
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let hasCustomAssemblyFormat = 1;
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let hasVerifier = 1;
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let skipDefaultBuilders = 1;
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let builders = [
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OpBuilder<(ins)>,
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];
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let extraClassDeclaration = [{
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::llvm::iterator_range<::mlir::Block::iterator> getYieldingOps();
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::mlir::OpResult getParentResult(int64_t idx);
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}];
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}
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def SpatYieldOp : SpatOp<"yield", [Terminator]> {
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let summary = "Yield results from a compute region";
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@@ -110,14 +153,14 @@ def SpatChannelSendOp : SpatOp<"channel_send", []> {
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let summary = "Send a tensor through a logical channel";
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let arguments = (ins
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I64Attr:$channelId,
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I32Attr:$sourceCoreId,
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I32Attr:$targetCoreId,
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Index:$channelId,
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Index:$sourceCoreId,
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Index:$targetCoreId,
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SpatTensor:$input
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);
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let assemblyFormat = [{
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$input attr-dict `:` type($input)
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$input `channel` $channelId `from` $sourceCoreId `to` $targetCoreId attr-dict `:` type($input)
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}];
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}
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@@ -125,9 +168,9 @@ def SpatChannelReceiveOp : SpatOp<"channel_receive", []> {
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let summary = "Receive a tensor from a logical channel";
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let arguments = (ins
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I64Attr:$channelId,
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I32Attr:$sourceCoreId,
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I32Attr:$targetCoreId
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Index:$channelId,
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Index:$sourceCoreId,
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Index:$targetCoreId
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);
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let results = (outs
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@@ -135,31 +178,33 @@ def SpatChannelReceiveOp : SpatOp<"channel_receive", []> {
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);
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let assemblyFormat = [{
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attr-dict `:` type($output)
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`channel` $channelId `from` $sourceCoreId `to` $targetCoreId attr-dict `:` type($output)
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}];
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}
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def SpatChannelSendTensorOp : SpatOp<"channel_send_tensor", []> {
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def SpatChannelSendTensorOp : SpatOp<"channel_send_tensor", [AttrSizedOperandSegments]> {
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let summary = "Send equal contiguous chunks of one tensor through logical channels";
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let arguments = (ins
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DenseI64ArrayAttr:$channelIds,
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DenseI32ArrayAttr:$sourceCoreIds,
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DenseI32ArrayAttr:$targetCoreIds,
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Variadic<Index>:$channelIds,
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Variadic<Index>:$sourceCoreIds,
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Variadic<Index>:$targetCoreIds,
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SpatTensor:$input
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);
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let hasVerifier = 1;
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let hasCustomAssemblyFormat = 1;
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let assemblyFormat = [{
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$input `channels` `(` $channelIds `)` `from` `(` $sourceCoreIds `)` `to` `(` $targetCoreIds `)` attr-dict `:` type($input)
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}];
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}
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def SpatChannelReceiveTensorOp : SpatOp<"channel_receive_tensor", []> {
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def SpatChannelReceiveTensorOp : SpatOp<"channel_receive_tensor", [AttrSizedOperandSegments]> {
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let summary = "Receive equal contiguous chunks of one tensor from logical channels";
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let arguments = (ins
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DenseI64ArrayAttr:$channelIds,
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DenseI32ArrayAttr:$sourceCoreIds,
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DenseI32ArrayAttr:$targetCoreIds
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Variadic<Index>:$channelIds,
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Variadic<Index>:$sourceCoreIds,
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Variadic<Index>:$targetCoreIds
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);
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let results = (outs
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@@ -167,44 +212,50 @@ def SpatChannelReceiveTensorOp : SpatOp<"channel_receive_tensor", []> {
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);
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let hasVerifier = 1;
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let hasCustomAssemblyFormat = 1;
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let assemblyFormat = [{
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`channels` `(` $channelIds `)` `from` `(` $sourceCoreIds `)` `to` `(` $targetCoreIds `)` attr-dict `:` type($output)
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}];
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}
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def SpatChannelSendBatchOp : SpatOp<"channel_send_batch", []> {
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def SpatChannelSendBatchOp : SpatOp<"channel_send_batch", [AttrSizedOperandSegments]> {
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let summary = "Send per-lane tensors through logical channels in a batch body";
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let arguments = (ins
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DenseI64ArrayAttr:$channelIds,
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DenseI32ArrayAttr:$sourceCoreIds,
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DenseI32ArrayAttr:$targetCoreIds,
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Variadic<Index>:$channelIds,
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Variadic<Index>:$sourceCoreIds,
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Variadic<Index>:$targetCoreIds,
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SpatTensor:$input
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);
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let hasVerifier = 1;
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let hasCustomAssemblyFormat = 1;
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let assemblyFormat = [{
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$input `channels` `(` $channelIds `)` `from` `(` $sourceCoreIds `)` `to` `(` $targetCoreIds `)` attr-dict `:` type($input)
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}];
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}
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def SpatChannelSendTensorBatchOp : SpatOp<"channel_send_tensor_batch", []> {
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def SpatChannelSendTensorBatchOp : SpatOp<"channel_send_tensor_batch", [AttrSizedOperandSegments]> {
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let summary = "Send equal contiguous chunks of one per-lane tensor through logical channels in a batch body";
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let arguments = (ins
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DenseI64ArrayAttr:$channelIds,
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DenseI32ArrayAttr:$sourceCoreIds,
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DenseI32ArrayAttr:$targetCoreIds,
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Variadic<Index>:$channelIds,
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Variadic<Index>:$sourceCoreIds,
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Variadic<Index>:$targetCoreIds,
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SpatTensor:$input
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);
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let hasVerifier = 1;
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let hasCustomAssemblyFormat = 1;
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let assemblyFormat = [{
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$input `channels` `(` $channelIds `)` `from` `(` $sourceCoreIds `)` `to` `(` $targetCoreIds `)` attr-dict `:` type($input)
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}];
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}
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def SpatChannelReceiveBatchOp : SpatOp<"channel_receive_batch", []> {
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def SpatChannelReceiveBatchOp : SpatOp<"channel_receive_batch", [AttrSizedOperandSegments]> {
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let summary = "Receive a per-lane tensor through logical channels in a batch body";
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let arguments = (ins
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DenseI64ArrayAttr:$channelIds,
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DenseI32ArrayAttr:$sourceCoreIds,
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DenseI32ArrayAttr:$targetCoreIds
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Variadic<Index>:$channelIds,
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Variadic<Index>:$sourceCoreIds,
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Variadic<Index>:$targetCoreIds
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);
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let results = (outs
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@@ -212,16 +263,18 @@ def SpatChannelReceiveBatchOp : SpatOp<"channel_receive_batch", []> {
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);
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let hasVerifier = 1;
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let hasCustomAssemblyFormat = 1;
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let assemblyFormat = [{
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`channels` `(` $channelIds `)` `from` `(` $sourceCoreIds `)` `to` `(` $targetCoreIds `)` attr-dict `:` type($output)
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}];
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}
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def SpatChannelReceiveTensorBatchOp : SpatOp<"channel_receive_tensor_batch", []> {
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def SpatChannelReceiveTensorBatchOp : SpatOp<"channel_receive_tensor_batch", [AttrSizedOperandSegments]> {
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let summary = "Receive equal contiguous chunks of one per-lane tensor through logical channels in a batch body";
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let arguments = (ins
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DenseI64ArrayAttr:$channelIds,
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DenseI32ArrayAttr:$sourceCoreIds,
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DenseI32ArrayAttr:$targetCoreIds
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Variadic<Index>:$channelIds,
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Variadic<Index>:$sourceCoreIds,
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Variadic<Index>:$targetCoreIds
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);
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let results = (outs
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@@ -229,7 +282,9 @@ def SpatChannelReceiveTensorBatchOp : SpatOp<"channel_receive_tensor_batch", []>
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);
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let hasVerifier = 1;
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let hasCustomAssemblyFormat = 1;
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let assemblyFormat = [{
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`channels` `(` $channelIds `)` `from` `(` $sourceCoreIds `)` `to` `(` $targetCoreIds `)` attr-dict `:` type($output)
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}];
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}
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//===----------------------------------------------------------------------===//
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@@ -240,7 +295,7 @@ def SpatVMMOp : SpatOp<"wvmm", []> {
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let summary = "Vector-matrix multiplication within a weighted compute operation";
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let arguments = (ins
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I32Attr:$weightIndex,
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SpatTensor:$weight,
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SpatTensor:$input
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);
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@@ -251,7 +306,7 @@ def SpatVMMOp : SpatOp<"wvmm", []> {
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let hasVerifier = 1;
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let assemblyFormat = [{
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`(` $input `)` attr-dict `:` type($input) `->` type($output)
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`[` $weight `]` `(` $input `)` attr-dict `:` `(` type($weight) `,` type($input) `)` `->` type($output)
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}];
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}
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@@ -259,7 +314,7 @@ def SpatMVMOp : SpatOp<"Wmvm", []> {
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let summary = "Matrix-vector multiplication within a weighted compute operation";
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let arguments = (ins
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I32Attr:$weightIndex,
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SpatTensor:$weight,
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SpatTensor:$input
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);
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@@ -270,7 +325,7 @@ def SpatMVMOp : SpatOp<"Wmvm", []> {
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let hasVerifier = 1;
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let assemblyFormat = [{
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`(` $input `)` attr-dict `:` type($input) `->` type($output)
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`[` $weight `]` `(` $input `)` attr-dict `:` `(` type($weight) `,` type($input) `)` `->` type($output)
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}];
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}
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