Broken pim-sim commit

backend-simulators/pim/pim-simulator/src/lib/instruction_set/isa.rs

@@ -16,7 +16,7 @@ use anyhow::{Context, Result, ensure};
 use rayon::prelude::*;
 
 use paste::paste;
-use std::{borrow::Cow, cell::OnceCell, collections::HashMap};
+use std::{borrow::Cow, cell::OnceCell, collections::HashMap };
 use std::{collections::HashSet, sync::LazyLock};
 
 macro_rules! add_name {
@@ -35,7 +35,7 @@ macro_rules! add_name_simd {
     };
 }
 
-static NAMES: LazyLock<HashMap<usize, &'static str>> = LazyLock::new(|| {
+pub static NAMES: LazyLock<HashMap<usize, &'static str>> = LazyLock::new(|| {
     let mut hash = HashMap::new();
     add_name!(hash, sldi);
     add_name!(hash, sld);
@@ -775,10 +775,19 @@ pub fn lmv(cores: &mut CPU, data: InstructionData) -> Result<InstructionStatus>
     Ok(InstructionStatus::Completed)
 }
 
+pub fn isa_send(functor : usize) -> bool{
+    (send as *const () as usize) == functor
+}
+
 pub fn send(cores: &mut CPU, data: InstructionData) -> Result<InstructionStatus> {
     Ok(InstructionStatus::Sending(data))
 }
 
+pub fn isa_recv(functor : usize) -> bool{
+    println!("{} {} ", functor, (recv as *const () as usize));
+    (recv as *const () as usize) == functor
+}
+
 pub fn recv(cores: &mut CPU, data: InstructionData) -> Result<InstructionStatus> {
     Ok(InstructionStatus::Reciving(data))
 }

backend-simulators/pim/pim-simulator/src/lib/instruction_set/mod.rs

@@ -14,7 +14,7 @@ pub mod helper;
 #[derive(Clone, Copy, Debug)]
 pub struct Instruction {
     pub data: InstructionData,
-    functor: InstructionType,
+    pub functor: InstructionType,
 }
 
 #[derive(Debug, Clone, Copy, Default)]

backend-simulators/pim/pim-simulator/src/lib/json_to_instruction/json_to_executor.rs

@@ -1,11 +1,15 @@
 use core::panic;
-use std::collections::HashMap;
+use std::io::{Read, Write};
+use std::{collections::HashMap, fs::File, io::BufReader};
 
-use serde_json::{Map, Value};
+use serde_json::{Deserializer, Map, Value};
 
 use crate::{
     CoreInstructionsBuilder, Executable,
-    cpu::{CPU, crossbar::{self, Crossbar}},
+    cpu::{
+        CPU,
+        crossbar::{self, Crossbar},
+    },
     instruction_set::{
         InstructionsBuilder,
         instruction_data::{self, InstructionData, InstructionDataBuilder},
@@ -14,11 +18,10 @@ use crate::{
     memory_manager::type_traits::TryToUsize,
 };
 
-
 pub fn json_to_executor<'a, 'b>(
     config: Value,
-    mut cores: impl Iterator<Item = &'b Value>,
-    crossbars : Vec<Vec<&'a Crossbar>>
+    mut cores: Vec<BufReader<File>>,
+    crossbars: Vec<Vec<&'a Crossbar>>,
 ) -> Executable<'a> {
     let cell_precision = config.get("cell_precision").unwrap().as_i64().unwrap() as i32;
     let core_cnt = config.get("core_cnt").unwrap().as_i64().unwrap() as i32 - 1;
@@ -29,19 +32,18 @@ pub fn json_to_executor<'a, 'b>(
 
     let mut cpu = CPU::new(core_cnt, crossbars);
     let mut core_insts_builder = CoreInstructionsBuilder::new(core_cnt as usize);
-    cores.next();
+    // Note: cores[0] is intentionally empty and discarded
     for core_indx in 1..=core_cnt {
         let mut insts_builder = InstructionsBuilder::new();
         let mut inst_data_builder = InstructionDataBuilder::new();
         inst_data_builder.set_core_indx(core_indx).fix_core_indx();
-        let json_core = cores
-            .next()
-            .unwrap_or_else(|| panic!("cores files less than {}", core_indx ));
-        let json_core_insts = json_core
-            .as_array()
-            .unwrap_or_else(|| panic!("core{} has not a list of instruction", core_indx));
-        for json_inst in json_core_insts {
-            json_isa::json_to_instruction(&mut insts_builder, &mut inst_data_builder, json_inst);
+        let stream = Deserializer::from_reader(&mut cores[core_indx as usize]).into_iter::<Value>();
+
+        for (i, json_inst_result) in stream.enumerate() {
+            let json_inst = json_inst_result.expect("Failed to parse instruction");
+            // Pass the single Value to your parser
+            json_isa::json_to_instruction(&mut insts_builder, &mut inst_data_builder, &json_inst);
+            drop(json_inst);
         }
         core_insts_builder.set_core(core_indx, insts_builder.build());
     }

backend-simulators/pim/pim-simulator/src/lib/pimcore.rs

@@ -4,7 +4,10 @@ use std::time::{Duration, SystemTime};
 
 use crate::{
     cpu::CPU,
-    instruction_set::{Instruction, InstructionStatus, Instructions, isa::functor_to_name},
+    instruction_set::{
+        Instruction, InstructionStatus, Instructions,
+        isa::{NAMES, functor_to_name, isa_recv, isa_send},
+    },
     memory_manager::type_traits::TryToUsize,
     send_recv::{SendRecv, handle_send_recv},
     tracing::TRACER,
@@ -144,8 +147,9 @@ impl<'a> Executable<'a> {
                     cpu_progressed = 0;
                     *program_counter += 1;
                 }
-                if (now.elapsed().unwrap() > Duration::from_secs(1)) {
-                    print_status(&cores_instructions);
+                if (now.elapsed().unwrap() > Duration::from_secs(5)) {
+                    print_status(cores_instructions);
+                    check_cycle(cpu, cores_instructions, send_recv);
                     now = SystemTime::now();
                 }
             }
@@ -170,7 +174,7 @@ impl<'a> Executable<'a> {
         }
         print_status(cores_instructions);
 
-    #[cfg(feature = "profile_time")]
+        #[cfg(feature = "profile_time")]
         TRACER.lock().unwrap().report();
     }
 
@@ -193,6 +197,46 @@ impl<'a> Executable<'a> {
     }
 }
 
+fn check_cycle(cpu: &mut CPU, cores_instructions: &[CoreInstructions], send_recv: &mut SendRecv) {
+    //println!("PRINTAAA");
+    //*PRINTAAA.lock().unwrap() = true;
+    //(inst.functor)(cpu, inst.data);
+    //*PRINTAAA.lock().unwrap() = false;
+    //
+    
+    println!("NAMES");
+    for (a,n) in NAMES.iter(){
+        println!("{} {}", a, n);
+    }
+
+    let mut i = 0;
+    for CoreInstructions {
+        instructions,
+        program_counter,
+    } in cores_instructions
+    {
+        if *program_counter >= instructions.len() {
+            continue;
+        }
+        let Instruction { data, functor } = instructions[*program_counter];
+        let functor_address = functor as usize;
+        
+        print!("Core {} ", i);
+        i += 1;
+            match (isa_recv(functor_address), isa_send(functor_address)) {
+                (true, false) => {
+                    let (receiver, sender) = data.get_core_immcore();
+                    println!("{} <- {}", receiver, sender);
+                }
+                (false, true) => {
+                    let (sender, receiver) = data.get_core_immcore();
+                    println!("{} -> {}", receiver, sender);
+                }
+                _ => {}
+            }
+    }
+}
+
 fn handle_wait_sync<'a, 'b, 'c>(
     cpu: &'b mut CPU<'a>,
     core_instructions: &'c mut [CoreInstructions],