better throughput in pipeline mode

.agents/invariants/PIMSIM_NN_ORACLE_INVARIANT.md

@@ -0,0 +1,22 @@
+# pimsim-nn Oracle Invariant
+
+`backend-simulators/pim/pimsim-nn` is the performance oracle. Its simulation
+behavior defines the hardware model used for Raptor/PIMCOMP comparisons.
+
+## Required invariant
+
+- Do not add instruction or operator support to pimsim-nn.
+- Changes to pimsim-nn must preserve simulation behavior exactly. Acceptable
+  changes are limited to behavior-neutral maintenance proven not to alter
+  simulated timing, scheduling, power, energy, or supported input programs.
+- Unsupported pimsim-nn operations must remain unsupported; do not approximate
+  their timing or map them onto another operation.
+- Adapt compiler inputs to the oracle instead. For YOLO, use
+  `validation/networks/pimcomp_models/yolo11n/yolo11n-pimsim-nn.onnx`, the
+  dedicated pimsim-ready performance artifact with Softmax operations removed.
+  Use `validation/networks/yolo11n/depth_51/yolo11n_depth_51.onnx` for YOLO
+  functional validation; removing Softmax changes the model's numerical
+  behavior, so the pimsim-ready artifact is not a correctness reference.
+
+Any proposed pimsim-nn behavior change requires explicit user authorization and
+must not be introduced as part of a compiler optimization.

.agents/invariants/PIPELINE_SCHEDULING_INVARIANT.md

@@ -0,0 +1,53 @@
+# Pipeline Scheduling Invariant
+
+## Scope
+
+This invariant applies to pipeline stage partitioning, physical-core
+assignment, scheduled materialization, deferred transfers, and pipeline
+synchronization.
+
+## Invariant
+
+A scheduled compute operation and all of its lanes belong to exactly one
+pipeline stage. An operation may consume results produced in its own stage or
+the immediately preceding stage only. Therefore every compute-graph edge from
+stage `S` targets stage `S` or `S + 1`; backward edges and dependencies that
+skip a stage are invalid.
+
+Dynamic function inputs are stage-zero sources. Any operation that directly
+consumes one must belong to stage 0. A later stage may consume that data only
+through an explicit result forwarded by the preceding stage.
+
+Each logical core belongs to exactly one stage capacity range before physical
+placement. Those ranges cover every core but may have different sizes when the
+initial partitioner predicts a lower maximum stage interval. Physical placement
+may map a stage to arbitrary core IDs using the injected target topology.
+Synchronization and deferred transfers consume the explicit stage identity;
+they must not infer it from a physical core number after placement.
+
+## Ownership
+
+Logical PEFT remains pipeline-agnostic. Stage partitioning is the first phase
+of pipeline scheduling and owns this invariant. It must construct a valid
+operation-level partition before physical-core packing. Operations split for
+physical capacity retain one shared stage identity. Repacking may move work
+only within its assigned stage. Deferred-transfer planning and
+synchronization consume the verified stage assignment; they must not repair
+or reinterpret it.
+
+## Verification
+
+Before scheduled materialization, verify that:
+
+- every compute instance has one valid physical core and stage;
+- all lanes of one compute operation have the same stage;
+- every direct dynamic-function-input consumer belongs to stage 0;
+- every compute-graph edge stays within a stage or advances exactly one stage;
+- every stage-local resident-weight set fits its assigned physical core; and
+- stage capacities cover all logical cores exactly once; and
+- physical placement is a permutation of all target cores.
+
+Pipeline scheduling tests must include an uneven physical-core layout and a
+graph with a long-lived dependency that would cross multiple naive stage
+cuts. End-to-end validation must preserve functional results and exercise the
+existing synchronization lowering without simulator changes.

AGENTS.md

@@ -6,6 +6,8 @@ Before modifying the relevant subsystem, read:
 
 * `.agents/invariants/GRAPH_COMPUTE_BATCH_INVARIANT.md`
 * `.agents/invariants/PERFORMANCE_OPTIMIZATION_INVARIANT.md`
+* `.agents/invariants/PIMSIM_NN_ORACLE_INVARIANT.md`
+* `.agents/invariants/PIPELINE_SCHEDULING_INVARIANT.md`
 * `.agents/invariants/SPATIAL_TARGET_GENERALITY_INVARIANT.md`
 * Build commands:
   * `cmake --build ./build_release`

src/PIM/Compiler/PimCodeGen.cpp

@@ -544,11 +544,23 @@ void PimCodeGen::setupRdRs1(size_t rdAddress, size_t rdOffset, size_t rs1Address
   genSetRegisterImmediateUnsigned(1, pim::checkedAddOrCrash(rs1Address, rs1Offset, "rs1 address"));
 }
 
-void PimCodeGen::setupRdRs1Rs2(
+std::array<uint8_t, 3> PimCodeGen::setupRdRs1Rs2(
   size_t rdAddress, size_t rdOffset, size_t rs1Address, size_t rs1Offset, size_t rs2Address, size_t rs2Offset) const {
-  genSetRegisterImmediateUnsigned(0, pim::checkedAddOrCrash(rdAddress, rdOffset, "rd address"));
+  size_t rd = pim::checkedAddOrCrash(rdAddress, rdOffset, "rd address");
-  genSetRegisterImmediateUnsigned(1, pim::checkedAddOrCrash(rs1Address, rs1Offset, "rs1 address"));
+  size_t rs1 = pim::checkedAddOrCrash(rs1Address, rs1Offset, "rs1 address");
-  genSetRegisterImmediateUnsigned(2, pim::checkedAddOrCrash(rs2Address, rs2Offset, "rs2 address"));
+  size_t rs2 = pim::checkedAddOrCrash(rs2Address, rs2Offset, "rs2 address");
+  genSetRegisterImmediateUnsigned(0, rd);
+  uint8_t rs1Register = 0;
+  if (rd != rs1) {
+    genSetRegisterImmediateUnsigned(1, rs1);
+    rs1Register = 1;
+  }
+  if (rd == rs2)
+    return {0, rs1Register, 0};
+  if (rs1 == rs2)
+    return {0, rs1Register, rs1Register};
+  genSetRegisterImmediateUnsigned(2, rs2);
+  return {0, rs1Register, 2};
 }
 
 void PimCodeGen::emitMemCopyOp(pim_binary::Opcode opcode,
@@ -664,13 +676,13 @@ void PimCodeGen::codeGenVMVOp(pim::PimVMVOp vmvOp, const StaticValueKnowledge& k
   auto sourceType = cast<ShapedType>(vmvOp.getSource().getType());
   int32_t bitwidth = getVectorElementBitwidthOrCrash(sourceType);
   ensureVectorBitwidth(bitwidth, bitwidth);
-  setupRdRs1Rs2(addressOf(vmvOp.getTarget(), knowledge), *targetOffset,
+  auto registers = setupRdRs1Rs2(addressOf(vmvOp.getTarget(), knowledge), *targetOffset,
                                  addressOf(vmvOp.getSource(), knowledge), *sourceOffset, 0, *sourceStride);
   pim_binary::InstructionRecord instruction;
   instruction.opcode = pim_binary::Opcode::vmv;
-  instruction.rd = 0;
+  instruction.rd = registers[0];
-  instruction.r1 = 1;
+  instruction.r1 = registers[1];
-  instruction.r2OrImm = 2;
+  instruction.r2OrImm = registers[2];
   instruction.generic3 = vmvOp.getLength();
   emitInstruction(instruction);
 }
@@ -780,12 +792,13 @@ void PimCodeGen::emitBinaryVectorOp(pim_binary::Opcode opcode,
   auto inputType = cast<ShapedType>(lhs.getType());
   ensureVectorBitwidth(getVectorElementBitwidthOrCrash(inputType),
                        getVectorElementBitwidthOrCrash(cast<ShapedType>(output.getType())));
-  setupRdRs1Rs2(addressOf(output, knowledge), 0, addressOf(lhs, knowledge), 0, addressOf(rhs, knowledge), 0);
+  auto registers = setupRdRs1Rs2(
+    addressOf(output, knowledge), 0, addressOf(lhs, knowledge), 0, addressOf(rhs, knowledge), 0);
   pim_binary::InstructionRecord instruction;
   instruction.opcode = opcode;
-  instruction.rd = 0;
+  instruction.rd = registers[0];
-  instruction.r1 = 1;
+  instruction.r1 = registers[1];
-  instruction.r2OrImm = 2;
+  instruction.r2OrImm = registers[2];
   instruction.generic3 = getVectorElementCountOrCrash(inputType);
   emitInstruction(instruction);
 }

src/PIM/Compiler/PimCodeGen.hpp

@@ -176,7 +176,7 @@ class PimCodeGen {
   void genSetRegisterImmediateUnsigned(size_t registerNumber, size_t immediate) const;
   void setupRd(size_t rdAddress, size_t rdOffset) const;
   void setupRdRs1(size_t rdAddress, size_t rdOffset, size_t rs1Address, size_t rs1Offset) const;
-  void setupRdRs1Rs2(
+  std::array<uint8_t, 3> setupRdRs1Rs2(
     size_t rdAddress, size_t rdOffset, size_t rs1Address, size_t rs1Offset, size_t rs2Address, size_t rs2Offset) const;
 
   void emitMemCopyOp(pim_binary::Opcode opcode,

src/PIM/Compiler/PimCompilerOptions.cpp

@@ -140,8 +140,8 @@ void verifyExplicitPimCoreCount() {
 void verifyPimPipelineStages() {
   if (pipelineStages.getValue() == 0)
     llvm::report_fatal_error("PIM compilation requires --pipeline to be positive");
-  if (static_cast<size_t>(coresCount.getValue()) % pipelineStages.getValue() != 0)
+  if (static_cast<size_t>(coresCount.getValue()) < pipelineStages.getValue())
-    llvm::report_fatal_error("PIM compilation requires --core-count to be divisible by --pipeline");
+    llvm::report_fatal_error("PIM compilation requires --pipeline not to exceed --core-count");
   if (crossbarCountInCore.getValue()
       > std::numeric_limits<size_t>::max() / pipelineStages.getValue())
     llvm::report_fatal_error("PIM compilation --crossbar-count * --pipeline overflows");

src/PIM/Conversion/ONNXToSpatial/Patterns/Math/ReduceMean.cpp

@@ -370,6 +370,14 @@ struct ReduceMeanToSpatialCompute : OpConversionPattern<ReduceMeanOp> {
     Location loc = reduceMeanOp.getLoc();
     RankedTensorType leafType = getAllOnesType(inputType, resultType.getElementType());
     RankedTensorType keepdimsType = getKeepdimsType(inputType, resultType.getElementType(), reducedAxes);
+    if (semantics->keepdims != 0 && inputType.getRank() == 4
+        && inputType.getDimSize(0) == 1 && semantics->axes == ArrayRef<int64_t>({2, 3})
+        && resultType == keepdimsType) {
+      auto plan = spatial::SpatGlobalAveragePoolPlanOp::create(
+        rewriter, loc, resultType, adaptor.getData(), spatial::getNCHWLayout(rewriter.getContext()));
+      rewriter.replaceOp(reduceMeanOp, plan.getResult());
+      return success();
+    }
     int64_t laneCount = 1;
     for (auto [dim, isReduced] : llvm::zip_equal(keepdimsType.getShape(), reducedAxes)) {
       if (isReduced)

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/DeferredCommunicationRealization.cpp

@@ -34,7 +34,9 @@ static LogicalResult verifyNoEscapingRegionValues(Operation* owner, StringRef ph
                               << escapingUser->getName() << " at " << escapingUser->getLoc();
 }
 
-static LogicalResult placeLogicalProcessorsOnPhysicalCores(DeferredTransferPlan& plan, const SchedulingTarget& target) {
+static LogicalResult placeLogicalProcessorsOnPhysicalCores(
+    DeferredTransferPlan& plan, const SchedulingTarget& target,
+    size_t pipelineStages) {
   std::vector<Cost> logicalTrafficFlits(target.processorCount * target.processorCount, 0);
   for (const std::unique_ptr<DeferredExchangePlan>& exchange : plan.exchanges)
     for (const ExternalTransferFamily& transfer : exchange->external) {
@@ -55,8 +57,15 @@ static LogicalResult placeLogicalProcessorsOnPhysicalCores(DeferredTransferPlan&
       }
     }
 
+  std::vector<size_t> placementGroups;
+  if (pipelineStages > 1) {
+    if (plan.processorStages.size() != target.processorCount)
+      return failure();
+    placementGroups = plan.processorStages;
+  }
   std::vector<size_t> physicalCoreForLogicalProcessor =
-    mapLogicalProcessorsToPhysicalCores(logicalTrafficFlits, target);
+    mapLogicalProcessorsToPhysicalCores(
+      logicalTrafficFlits, target, placementGroups);
   auto getPhysicalCore = [&](int64_t logicalProcessor) {
     assert(logicalProcessor >= 0 && static_cast<size_t>(logicalProcessor) < physicalCoreForLogicalProcessor.size()
            && "logical processor is outside the scheduling target");
@@ -218,7 +227,8 @@ LogicalResult realizeDeferredCommunication(func::FuncOp funcOp,
     funcOp, materialization, pipelineStages, target.processorCount);
   if (failed(transfers))
     return funcOp.emitOpError("phase 2 failed to build symbolic transfer families");
-  if (failed(placeLogicalProcessorsOnPhysicalCores(*transfers, target)))
+  if (failed(placeLogicalProcessorsOnPhysicalCores(
+        *transfers, target, pipelineStages)))
     return failure();
   if (transfers->pipelineHostBufferBytes != 0) {
     auto bytes = pim::checkedCast<int64_t>(

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/DeferredTransferPlanning.cpp

@@ -32,9 +32,11 @@ static LogicalResult collectScheduledOperations(
     DeferredTransferPlan &plan,
     size_t pipelineStageCount,
     size_t processorCount) {
-  if (pipelineStageCount == 0 || processorCount % pipelineStageCount != 0)
+  if (pipelineStageCount == 0
+      || (pipelineStageCount > 1
+          && materialization.processorStages.size() != processorCount))
     return failure();
-  size_t stageSize = processorCount / pipelineStageCount;
+  plan.processorStages = materialization.processorStages;
   unsigned nextStream = 0;
   for (const ScheduledMaterializationRecord &record :
        materialization.materializedSchedules) {
@@ -56,8 +58,12 @@ static LogicalResult collectScheduledOperations(
       if (core >= processorCount)
         return op.emitOpError("phase 2 scheduled core is outside the target");
       info.cores.push_back(core);
-      if (pipelineStageCount > 1)
+      if (pipelineStageCount > 1) {
-        info.pipelineStages.push_back(core / stageSize);
+        size_t stage = materialization.processorStages[core];
+        if (stage >= pipelineStageCount)
+          return op.emitOpError("phase 2 scheduled core has an invalid pipeline stage");
+        info.pipelineStages.push_back(stage);
+      }
     }
     for (size_t lane = 0; lane < info.cores.size(); ++lane)
       info.streamIds.push_back(nextStream++);

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/DeferredTransferPlanning.hpp

@@ -8,6 +8,7 @@
 namespace onnx_mlir::spatial {
 
 struct DeferredTransferPlan {
+  std::vector<size_t> processorStages;
   llvm::SmallVector<ScheduledInfo, 0> scheduled;
   llvm::SmallVector<std::unique_ptr<ProducedValue>> producedStorage;
   llvm::DenseMap<int64_t, llvm::SmallVector<ProducedValue*>> producedByGraph;

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/ScheduledComputeMaterialization.cpp

@@ -808,7 +808,9 @@ materializeScheduledCompute(func::FuncOp funcOp,
     }
   }
 
-  return ScheduledComputeMaterializationResult {std::move(peftClassPlans), std::move(materializedSchedules), std::move(graphComputeToBlockMap)};
+  return ScheduledComputeMaterializationResult {
+    std::move(peftClassPlans), std::move(materializedSchedules),
+    std::move(graphComputeToBlockMap), schedule.processorStages};
 }
 
 

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/ScheduledComputeMaterialization.hpp

@@ -14,6 +14,7 @@ struct ScheduledComputeMaterializationResult {
   llvm::MapVector<size_t, PeftClassPlan> peftClassPlans;
   std::vector<ScheduledMaterializationRecord> materializedSchedules;
   DenseMap<GraphComputeBlockKey, Block *> graphComputeToBlockMap;
+  std::vector<size_t> processorStages;
 };
 
 FailureOr<BatchFragmentSpec>

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/ScheduledSpatialPasses.cpp

@@ -39,8 +39,9 @@ static SchedulingTarget getPipelineSchedulingTarget(
   if (pipelineStages == 1)
     return physicalTarget;
 
+  PipelineCoreLayout layout(physicalTarget.processorCount, pipelineStages);
   SchedulingTarget schedulingTarget = physicalTarget;
-  schedulingTarget.processorCount = physicalTarget.processorCount / pipelineStages;
+  schedulingTarget.processorCount = layout.getLogicalProcessorCount();
   schedulingTarget.residentWeightCapacity = checkedMultiply(
     physicalTarget.residentWeightCapacity, pipelineStages);
   schedulingTarget.interProcessorLatencyNs.assign(
@@ -88,7 +89,8 @@ struct ScheduleAndRealizeSpatialPass final
       signalPassFailure();
       return;
     }
-    if (pipelineStages == 0 || target.processorCount % pipelineStages != 0
+    PipelineCoreLayout pipelineLayout(target.processorCount, pipelineStages);
+    if (!pipelineLayout.isValid()
         || (pipelineStages > 1
             && target.synchronizationRegisterCount == 0)
         || target.residentWeightCapacity
@@ -115,19 +117,24 @@ struct ScheduleAndRealizeSpatialPass final
       scheduledGraph = analysis.getGraph();
       schedule = std::move(analysis.getResult());
       std::string pipelineError;
-      if (succeeded(applyPipelineScheduling(
+      if (pipelineStages > 1) {
-            scheduledGraph, schedule, pipelineStages, target, pipelineError)))
+        FailureOr<PipelineWorkloadPreparation> preparation =
-        break;
+          preparePipelineWorkload(
-      std::string splitError;
+            scheduledGraph, schedule, pipelineStages, target, pipelineError);
-      if (pipelineStages == 1
+        if (failed(preparation)) {
-          || failed(splitPipelineWorkload(
-                scheduledGraph, schedule, pipelineStages, target, splitError))) {
-        if (!splitError.empty())
-          pipelineError = splitError;
           moduleOp.emitError() << pipelineError;
           signalPassFailure();
           return;
         }
+        if (*preparation == PipelineWorkloadPreparation::Changed)
+          continue;
+      }
+      if (succeeded(applyPipelineScheduling(
+            scheduledGraph, schedule, pipelineStages, target, pipelineError)))
+        break;
+      moduleOp.emitError() << pipelineError;
+      signalPassFailure();
+      return;
     }
     PatternRewriter rewriter(moduleOp.getContext());
     FailureOr<ScheduledComputeMaterializationResult> materialization =

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/Scheduling/MergeSchedule.hpp

@@ -14,6 +14,7 @@ namespace spatial {
 
 struct MergeScheduleResult {
   size_t processorCount = 0;
+  std::vector<size_t> processorStages;
   std::vector<ComputeInstance> dominanceOrderCompute;
   llvm::DenseMap<ComputeInstance, size_t> computeToCpuMap;
   llvm::DenseMap<ComputeInstance, size_t> computeToCpuSlotMap;

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/Scheduling/PeftScheduler.cpp

@@ -244,11 +244,13 @@ FailureOr<LanePublicationSignatures> buildLanePublicationSignatures(SpatComputeB
 } // namespace
 
 std::vector<size_t> mapLogicalProcessorsToPhysicalCores(ArrayRef<Cost> logicalTrafficFlits,
-                                                        const SchedulingTarget& target) {
+                                                        const SchedulingTarget& target,
+                                                        ArrayRef<size_t> placementGroups) {
   const size_t processorCount = target.processorCount;
   assert(logicalTrafficFlits.size() == processorCount * processorCount
          && "logical traffic matrix must cover every processor pair");
-
+  assert((placementGroups.empty() || placementGroups.size() == processorCount)
+         && "physical placement groups must cover every processor");
   std::vector<size_t> physicalCoreForLogicalProcessor(processorCount);
   std::iota(physicalCoreForLogicalProcessor.begin(), physicalCoreForLogicalProcessor.end(), 0);
 
@@ -266,6 +268,10 @@ std::vector<size_t> mapLogicalProcessorsToPhysicalCores(ArrayRef<Cost> logicalTr
     for (size_t peerLogicalProcessor = 0; peerLogicalProcessor < processorCount; ++peerLogicalProcessor) {
       if (peerLogicalProcessor == logicalProcessor)
         continue;
+      if (!placementGroups.empty()
+          && placementGroups[peerLogicalProcessor]
+               != placementGroups[logicalProcessor])
+        continue;
       size_t physicalCore = physicalCoreForLogicalProcessor[logicalProcessor];
       size_t peerPhysicalCore = physicalCoreForLogicalProcessor[peerLogicalProcessor];
       Cost currentCost = 0;

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/Scheduling/PeftScheduler.hpp

@@ -29,7 +29,8 @@ inline Time getPeftTransferTime(const TransferCost& transferCost,
 MergeScheduleResult runPeftScheduler(const ComputeGraph& graph, const PeftScheduleOptions& options);
 
 std::vector<size_t> mapLogicalProcessorsToPhysicalCores(llvm::ArrayRef<Cost> logicalTrafficFlits,
-                                                        const SchedulingTarget& target);
+                                                        const SchedulingTarget& target,
+                                                        llvm::ArrayRef<size_t> placementGroups = {});
 
 } // namespace spatial
 } // namespace onnx_mlir

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/Scheduling/PipelineScheduling.cpp

@@ -1,7 +1,10 @@
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallBitVector.h"
 #include "llvm/ADT/STLExtras.h"
 
 #include <algorithm>
 #include <limits>
+#include <numeric>
 #include <optional>
 #include <queue>
 #include <tuple>
@@ -556,6 +559,10 @@ static LogicalResult splitBatchCompute(SpatGraphComputeBatch batch,
     return failure();
   if (failed(verifySplittableVmmUses(splitBody->vmms, error)))
     return failure();
+  if (!batch->hasAttr("pipeline.stage_group"))
+    batch->setAttr(
+      "pipeline.stage_group",
+      DistinctAttr::create(UnitAttr::get(batch.getContext())));
 
   size_t partCount = std::min(pipelineStages, splitBody->vmms.size());
   SmallVector<SmallVector<unsigned, 8>, 4> partitions =
@@ -601,10 +608,9 @@ static LogicalResult splitBatchCompute(SpatGraphComputeBatch batch,
   return success();
 }
 
-static LogicalResult splitPipelineWorkloadImpl(const ComputeGraph &graph,
+static FailureOr<PipelineWorkloadPreparation> preparePipelineWorkloadImpl(
-                                               const MergeScheduleResult &schedule,
+    const ComputeGraph &graph, const MergeScheduleResult &schedule,
-                                               size_t pipelineStages,
+    size_t pipelineStages, const SchedulingTarget &physicalTarget,
-                                               const SchedulingTarget &physicalTarget,
     std::string &error) {
   size_t groupSize = schedule.processorCount;
   std::vector<TaskList> tasksByCpu(groupSize);
@@ -654,7 +660,7 @@ static LogicalResult splitPipelineWorkloadImpl(const ComputeGraph &graph,
       std::string currentError;
       if (succeeded(splitBatchCompute(
             batch, pipelineStages, physicalTarget, currentError)))
-        return success();
+        return PipelineWorkloadPreparation::Changed;
       if (!currentError.empty())
         candidateError = currentError;
     }
@@ -663,7 +669,8 @@ static LogicalResult splitPipelineWorkloadImpl(const ComputeGraph &graph,
       : candidateError;
     return failure();
   }
-  return failure();
+
+  return PipelineWorkloadPreparation::Ready;
 }
 
 bool fits(const ComputeGraph& graph,
@@ -719,193 +726,585 @@ Cost findMaximumPackCost(const ComputeGraph& graph,
   return low;
 }
 
-static Cost getCoreCost(const TaskList &tasks, const TaskCosts &taskCosts) {
+static Cost findMaximumIndexedPackCost(
-  Cost cost = 0;
+    const TaskCosts &taskCosts,
-  for (size_t task : tasks)
+    const std::vector<TaskList> &taskWeightIds, size_t weightCount,
-    cost = checkedAdd(cost, taskCosts[task]);
+    const TaskList &tasks, size_t residentWeightCapacity,
-  return cost;
+    size_t maximumPacks) {
-}
+  Cost low = 0;
-
+  Cost high = 0;
-static Cost getStageMaximumAssemblyCost(
+  for (size_t task : tasks) {
-    const std::vector<TaskList> &tasksByCpu,
+    low = std::max(low, taskCosts[task]);
-    const TaskCosts &assemblyCosts, size_t groupSize, size_t stage) {
+    high = checkedAdd(high, taskCosts[task]);
-  Cost maximum = 0;
-  for (size_t cpu = stage * groupSize;
-      cpu < (stage + 1) * groupSize; ++cpu)
-    maximum = std::max(
-      maximum, getCoreCost(tasksByCpu[cpu], assemblyCosts));
-  return maximum;
-}
-
-static bool fitsResidentWeights(const ComputeGraph &graph,
-                                const TaskList &tasks, size_t candidate,
-                                size_t residentWeightCapacity) {
-  ResidentWeightSet weights;
-  for (size_t task : tasks)
-    insertResidentWeights(weights, graph.nodes[task].residentWeights);
-  return getResidentWeightUnionSize(
-           weights, graph.nodes[candidate].residentWeights)
-       <= residentWeightCapacity;
-}
-
-static void repackPipelineStage(
-    const ComputeGraph &graph, const TaskCosts &schedulingCosts,
-    const TaskCosts &assemblyCosts,
-    std::vector<TaskList> &tasksByCpu, size_t groupSize, size_t stage,
-    size_t residentWeightCapacity) {
-  TaskList tasks;
-  Cost originalMaximum = 0;
-  for (size_t cpu = stage * groupSize;
-       cpu < (stage + 1) * groupSize; ++cpu) {
-    llvm::append_range(tasks, tasksByCpu[cpu]);
-    originalMaximum = std::max(
-      originalMaximum,
-      getCoreCost(tasksByCpu[cpu], schedulingCosts));
   }
-  llvm::sort(tasks, [&](size_t lhs, size_t rhs) {
+  low = std::max(
+    low, high / maximumPacks + (high % maximumPacks != 0));
+
+  std::vector<size_t> seen(weightCount);
+  size_t generation = 0;
+  while (low < high) {
+    Cost middle = low + (high - low) / 2;
+    size_t packs = 1;
+    Cost cost = 0;
+    size_t packWeightCount = 0;
+    ++generation;
+    bool fits = true;
+    bool packEmpty = true;
+    for (size_t task : tasks) {
+      size_t addedWeights = 0;
+      for (size_t weight : taskWeightIds[task])
+        addedWeights += seen[weight] != generation;
+      Cost taskCost = taskCosts[task];
+      bool startsNewPack = !packEmpty
+        && (cost > middle - taskCost
+            || packWeightCount + addedWeights > residentWeightCapacity);
+      if (startsNewPack) {
+        if (++packs > maximumPacks) {
+          fits = false;
+          break;
+        }
+        cost = 0;
+        packWeightCount = 0;
+        ++generation;
+        packEmpty = true;
+      }
+      cost = checkedAdd(cost, taskCost);
+      for (size_t weight : taskWeightIds[task])
+        if (seen[weight] != generation) {
+          seen[weight] = generation;
+          ++packWeightCount;
+        }
+      packEmpty = false;
+    }
+    if (fits)
+      high = middle;
+    else
+      low = middle + 1;
+  }
+  return low;
+}
+
+static size_t findMinimumIndexedPackCount(
+    const std::vector<TaskList> &taskWeightIds, const TaskList &tasks,
+    size_t residentWeightCapacity) {
+  if (tasks.empty())
+    return 0;
+  size_t packs = 1;
+  TaskList weights;
+  for (size_t task : tasks) {
+    size_t unionSize = weights.size();
+    for (size_t weight : taskWeightIds[task])
+      unionSize += !llvm::is_contained(weights, weight);
+    if (!weights.empty() && unionSize > residentWeightCapacity) {
+      ++packs;
+      weights.clear();
+    }
+    for (size_t weight : taskWeightIds[task])
+      if (!llvm::is_contained(weights, weight))
+        weights.push_back(weight);
+  }
+  return packs;
+}
+
+struct PipelineGroup {
+  TaskList tasks;
+  TaskList successors;
+  size_t originalOrder = std::numeric_limits<size_t>::max();
+  TaskList weightIds;
+  bool consumesPipelineInput = false;
+};
+
+struct PipelineStageAssignment {
+  std::vector<size_t> taskStages;
+  std::vector<size_t> stageSizes;
+};
+
+static const TaskCosts &getPipelineBalanceCosts(
+    const ComputeGraph &graph, const PipelineTaskModel &model) {
+  for (size_t task = 0; task < graph.nodes.size(); ++task)
+    if (graph.nodes[task].instance.op && model.assemblyCosts[task] > 1
+        && !model.predecessors[task].empty())
+      return model.assemblyCosts;
+  return model.schedulingCosts;
+}
+
+static bool consumesPipelineInput(const ComputeGraphNode &node) {
+  if (!node.instance.op)
+    return false;
+  return llvm::any_of(getComputeInstanceInputs(node.instance),
+                      [](Value input) { return isa<BlockArgument>(input); });
+}
+
+static FailureOr<PipelineStageAssignment> assignPipelineStages(
+    const ComputeGraph &graph, const PipelineTaskModel &model,
+    const PipelineCoreLayout &layout, size_t residentWeightCapacity,
+    std::string &error) {
+  if (graph.nodes.empty())
+    return PipelineStageAssignment {
+      {}, std::vector<size_t>(layout.getStageCount(), 1)};
+  std::vector<size_t> tasksByOrder(graph.nodes.size());
+  std::iota(tasksByOrder.begin(), tasksByOrder.end(), 0);
+  llvm::sort(tasksByOrder, [&](size_t lhs, size_t rhs) {
     return graph.nodes[lhs].originalOrder < graph.nodes[rhs].originalOrder;
   });
 
-  std::vector<TaskList> packed(groupSize);
+  std::vector<PipelineGroup> groups;
-  std::vector<ResidentWeightSet> weights(groupSize);
+  std::vector<size_t> taskToGroup(graph.nodes.size());
-  TaskCosts loads(groupSize);
+  ResidentWeightSet indexedWeights;
-  TaskCosts assemblyLoads(groupSize);
+  std::vector<TaskList> taskWeightIds(graph.nodes.size());
+  for (size_t task : tasksByOrder)
+    for (const ResidentWeight &weight : graph.nodes[task].residentWeights) {
+      auto indexed = llvm::find(indexedWeights, weight);
+      size_t id = indexed - indexedWeights.begin();
+      if (indexed == indexedWeights.end()) {
+        id = indexedWeights.size();
+        indexedWeights.push_back(weight);
+      }
+      taskWeightIds[task].push_back(id);
+    }
+  llvm::DenseMap<Operation *, size_t> operationToGroup;
+  llvm::DenseMap<Attribute, size_t> splitOperationToGroup;
+  for (size_t task : tasksByOrder) {
+    Operation *operation = graph.nodes[task].instance.op;
+    Attribute splitGroup = operation
+      ? operation->getAttr("pipeline.stage_group")
+      : Attribute();
+    size_t group;
+    auto existingSplit = splitGroup
+      ? splitOperationToGroup.find(splitGroup)
+      : splitOperationToGroup.end();
+    auto existingOperation = operation && !splitGroup
+      ? operationToGroup.find(operation)
+      : operationToGroup.end();
+    if (existingSplit != splitOperationToGroup.end()) {
+      group = existingSplit->second;
+    } else if (existingOperation != operationToGroup.end()) {
+      group = existingOperation->second;
+    } else {
+      group = groups.size();
+      groups.emplace_back();
+      if (splitGroup)
+        splitOperationToGroup[splitGroup] = group;
+      else if (operation)
+        operationToGroup[operation] = group;
+    }
+    taskToGroup[task] = group;
+    PipelineGroup &pipelineGroup = groups[group];
+    pipelineGroup.tasks.push_back(task);
+    pipelineGroup.originalOrder = std::min(
+      pipelineGroup.originalOrder, graph.nodes[task].originalOrder);
+    pipelineGroup.consumesPipelineInput |=
+      consumesPipelineInput(graph.nodes[task]);
+    for (size_t weight : taskWeightIds[task])
+      if (!llvm::is_contained(pipelineGroup.weightIds, weight))
+        pipelineGroup.weightIds.push_back(weight);
+  }
+
+  std::vector<size_t> indegree(groups.size());
+  for (size_t task = 0; task < graph.nodes.size(); ++task)
+    for (size_t predecessor : model.predecessors[task]) {
+      size_t source = taskToGroup[predecessor];
+      size_t target = taskToGroup[task];
+      if (source == target
+          || llvm::is_contained(groups[source].successors, target))
+        continue;
+      groups[source].successors.push_back(target);
+      ++indegree[target];
+    }
+
+  auto laterOriginalOrder = [&](size_t lhs, size_t rhs) {
+    return groups[lhs].originalOrder > groups[rhs].originalOrder;
+  };
+  std::priority_queue<size_t, std::vector<size_t>, decltype(laterOriginalOrder)>
+    ready(laterOriginalOrder);
+  for (size_t group = 0; group < groups.size(); ++group)
+    if (indegree[group] == 0)
+      ready.push(group);
+
+  TaskList groupOrder;
+  while (!ready.empty()) {
+    size_t group = ready.top();
+    ready.pop();
+    groupOrder.push_back(group);
+    for (size_t successor : groups[group].successors)
+      if (--indegree[successor] == 0)
+        ready.push(successor);
+  }
+  if (groupOrder.size() != groups.size()) {
+    error = "pipeline scheduling cannot keep every operation in one stage "
+            "because the collapsed operation graph is cyclic";
+    return failure();
+  }
+
+  std::vector<size_t> position(groups.size());
+  for (auto [index, group] : llvm::enumerate(groupOrder))
+    position[group] = index;
+  size_t minimumStageZeroEnd = 0;
+  for (auto [index, group] : llvm::enumerate(groupOrder))
+    if (groups[group].consumesPipelineInput)
+      minimumStageZeroEnd = index + 1;
+  std::vector<size_t> furthestSuccessorBefore(groups.size() + 1, 0);
+  bool hasCrossingEdge = false;
+  size_t furthestSuccessor = 0;
+  for (size_t cut = 1; cut <= groups.size(); ++cut) {
+    size_t group = groupOrder[cut - 1];
+    for (size_t successor : groups[group].successors) {
+      if (position[successor] <= position[group]) {
+        error = "pipeline scheduling operation order is not topological";
+        return failure();
+      }
+      furthestSuccessor = std::max(furthestSuccessor, position[successor]);
+      hasCrossingEdge = true;
+    }
+    furthestSuccessorBefore[cut] = furthestSuccessor;
+  }
+
+  auto partitionGroups = [&](ArrayRef<size_t> coreCounts)
+      -> FailureOr<std::vector<size_t>> {
+    const Cost infinity = std::numeric_limits<Cost>::max();
+    const size_t noCut = std::numeric_limits<size_t>::max();
+    std::vector<std::vector<Cost>> best(
+      coreCounts.size() + 1,
+      std::vector<Cost>(groups.size() + 1, infinity));
+    std::vector<std::vector<size_t>> parent(
+      coreCounts.size() + 1,
+      std::vector<size_t>(groups.size() + 1, noCut));
+    std::vector<size_t> stageCostCache(coreCounts.size());
+    std::vector<size_t> cachedCoreCounts;
+    std::vector<std::vector<std::vector<Cost>>> segmentCostCaches;
+    for (auto [stage, coreCount] : llvm::enumerate(coreCounts)) {
+      auto cached = llvm::find(cachedCoreCounts, coreCount);
+      if (cached == cachedCoreCounts.end()) {
+        stageCostCache[stage] = segmentCostCaches.size();
+        cachedCoreCounts.push_back(coreCount);
+        segmentCostCaches.emplace_back(
+          groups.size() + 1,
+          std::vector<Cost>(groups.size() + 1, infinity));
+      } else {
+        stageCostCache[stage] = cached - cachedCoreCounts.begin();
+      }
+    }
+    best[0][0] = 0;
+
+    // ponytail: operation groups are small; replace this quadratic partition
+    // only if scheduling profiles show it matters.
+    for (size_t stage = 0; stage < coreCounts.size(); ++stage) {
+      size_t coreCount = coreCounts[stage];
+      size_t stageWeightCapacity = checkedMultiply(
+        coreCount, residentWeightCapacity);
+      for (size_t start = 0; start < groups.size(); ++start) {
+        if (best[stage][start] == infinity)
+          continue;
+        TaskList segmentTasks;
+        llvm::SmallBitVector segmentWeights(indexedWeights.size());
+        size_t segmentWeightCount = 0;
+        for (size_t end = start + 1; end <= groups.size(); ++end) {
+          const PipelineGroup &group = groups[groupOrder[end - 1]];
+          llvm::append_range(segmentTasks, group.tasks);
+          for (size_t weight : group.weightIds)
+            if (!segmentWeights.test(weight)) {
+              segmentWeights.set(weight);
+              ++segmentWeightCount;
+            }
+          if (segmentWeightCount > stageWeightCapacity)
+            break;
+          if (stage == 0 && end < minimumStageZeroEnd)
+            continue;
+          if (stage != 0 && hasCrossingEdge
+              && furthestSuccessorBefore[start] >= end)
+            continue;
+          Cost &segmentCost =
+            segmentCostCaches[stageCostCache[stage]][start][end];
+          if (segmentCost == infinity)
+            segmentCost = findMaximumIndexedPackCost(
+              model.schedulingCosts, taskWeightIds, indexedWeights.size(),
+              segmentTasks, residentWeightCapacity, coreCount);
+          Cost maximumLoad = std::max(best[stage][start], segmentCost);
+          if (maximumLoad < best[stage + 1][end]) {
+            best[stage + 1][end] = maximumLoad;
+            parent[stage + 1][end] = start;
+          }
+        }
+      }
+    }
+
+    size_t usedStages = 0;
+    Cost bestLoad = infinity;
+    for (size_t stages = 1; stages <= coreCounts.size(); ++stages)
+      if (best[stages][groups.size()] != infinity
+          && best[stages][groups.size()] <= bestLoad) {
+        bestLoad = best[stages][groups.size()];
+        usedStages = stages;
+      }
+    if (usedStages == 0) {
+      error = "pipeline scheduling cannot split operations into dependency-adjacent "
+              "stages within the physical crossbar limit";
+      return failure();
+    }
+
+    std::vector<size_t> groupStages(groups.size());
+    size_t end = groups.size();
+    for (size_t stage = usedStages; stage > 0; --stage) {
+      size_t start = parent[stage][end];
+      assert(start != noCut && "selected pipeline partition has no parent");
+      for (size_t position = start; position < end; ++position)
+        groupStages[groupOrder[position]] = stage - 1;
+      end = start;
+    }
+    return groupStages;
+  };
+
+  FailureOr<std::vector<size_t>> initialGroupStages =
+    partitionGroups(layout.getStageSizes());
+  if (failed(initialGroupStages))
+    return failure();
+
+  std::vector<TaskList> tasksByStage(layout.getStageCount());
+  for (size_t group : groupOrder)
+    llvm::append_range(
+      tasksByStage[(*initialGroupStages)[group]], groups[group].tasks);
+  std::vector<size_t> stageSizes(layout.getStageCount(), 1);
+  size_t assignedCores = stageSizes.size();
+  for (size_t stage = 0; stage < stageSizes.size(); ++stage) {
+    for (size_t task : tasksByStage[stage])
+      if (taskWeightIds[task].size() > residentWeightCapacity) {
+        error = "pipeline scheduling cannot fit one compute instance in a "
+                "physical core's crossbars";
+        return failure();
+      }
+    stageSizes[stage] = std::max(
+      stageSizes[stage], findMinimumIndexedPackCount(
+                           taskWeightIds, tasksByStage[stage],
+                           residentWeightCapacity));
+    assignedCores += stageSizes[stage] - 1;
+  }
+  if (assignedCores > layout.getProcessorCount()) {
+    error = "pipeline scheduling cannot fit dependency-adjacent stages "
+            "within the physical crossbar limit";
+    return failure();
+  }
+
+  const TaskCosts &balanceCosts = getPipelineBalanceCosts(graph, model);
+  auto getStageCost = [&](size_t stage, size_t coreCount) {
+    Cost schedulingCost = findMaximumIndexedPackCost(
+      model.schedulingCosts, taskWeightIds, indexedWeights.size(),
+      tasksByStage[stage], residentWeightCapacity, coreCount);
+    if (&balanceCosts == &model.schedulingCosts)
+      return schedulingCost;
+    Cost assemblyCost = findMaximumIndexedPackCost(
+      balanceCosts, taskWeightIds, indexedWeights.size(),
+      tasksByStage[stage], residentWeightCapacity, coreCount);
+    return std::max(schedulingCost, assemblyCost);
+  };
+  std::vector<Cost> stageCosts(stageSizes.size());
+  std::vector<Cost> nextStageCosts(stageSizes.size());
+  for (size_t stage = 0; stage < stageSizes.size(); ++stage)
+    stageCosts[stage] = getStageCost(stage, stageSizes[stage]);
+  for (size_t stage = 0; stage < stageSizes.size(); ++stage)
+    nextStageCosts[stage] = getStageCost(stage, stageSizes[stage] + 1);
+  while (assignedCores < layout.getProcessorCount()) {
+    size_t bestStage = 0;
+    Cost bestBenefit = 0;
+    for (size_t stage = 0; stage < stageSizes.size(); ++stage) {
+      Cost benefit = stageCosts[stage] - nextStageCosts[stage];
+      if (benefit > bestBenefit
+          || (benefit == bestBenefit
+              && (stageCosts[stage] > stageCosts[bestStage]
+                  || (stageCosts[stage] == stageCosts[bestStage]
+                      && stageSizes[stage] < stageSizes[bestStage])))) {
+        bestStage = stage;
+        bestBenefit = benefit;
+      }
+    }
+    ++stageSizes[bestStage];
+    stageCosts[bestStage] = nextStageCosts[bestStage];
+    nextStageCosts[bestStage] =
+      getStageCost(bestStage, stageSizes[bestStage] + 1);
+    ++assignedCores;
+  }
+  FailureOr<std::vector<size_t>> refinedGroupStages =
+    partitionGroups(stageSizes);
+  if (failed(refinedGroupStages))
+    return failure();
+  std::vector<size_t> taskStages(graph.nodes.size());
+  for (size_t task = 0; task < graph.nodes.size(); ++task)
+    taskStages[task] = (*refinedGroupStages)[taskToGroup[task]];
+  return PipelineStageAssignment {
+    std::move(taskStages), std::move(stageSizes)};
+}
+
+static bool packPipelineStage(
+    const ComputeGraph &graph, const TaskCosts &schedulingCosts,
+    const TaskCosts &assemblyCosts,
+    std::vector<TaskList> &tasksByCpu, const PipelineCoreLayout &layout,
+    ArrayRef<size_t> topologicalPosition, size_t stage,
+    size_t residentWeightCapacity, const SchedulingTarget &target,
+    std::vector<size_t> &taskCpus) {
+  PipelineStageRange range = layout.getStageRange(stage);
+  TaskList tasks;
+  for (size_t cpu = range.begin; cpu < range.begin + range.size; ++cpu)
+    llvm::append_range(tasks, tasksByCpu[cpu]);
+  llvm::sort(tasks, [&](size_t lhs, size_t rhs) {
+    return topologicalPosition[lhs] < topologicalPosition[rhs];
+  });
+  std::vector<TaskList> packed(range.size);
+  std::vector<ResidentWeightSet> weights(range.size);
+  TaskCosts loads(range.size);
+  TaskCosts assemblyLoads(range.size);
   for (size_t task : tasks) {
     std::optional<size_t> bestCore;
-    std::optional<std::tuple<Cost, Cost, size_t, size_t>> bestScore;
+    using PackScore = std::tuple<Cost, Time, Cost, Cost, size_t>;
-    for (size_t core = 0; core < groupSize; ++core) {
+    std::optional<PackScore> bestScore;
+    for (size_t core = 0; core < range.size; ++core) {
       size_t unionSize = getResidentWeightUnionSize(
         weights[core], graph.nodes[task].residentWeights);
       if (unionSize > residentWeightCapacity)
         continue;
       size_t addedWeights = unionSize - weights[core].size();
-      auto score = std::make_tuple(
+      Cost assemblyLoad = checkedAdd(
-        checkedAdd(assemblyLoads[core], assemblyCosts[task]),
+        assemblyLoads[core], assemblyCosts[task]);
-        checkedAdd(loads[core], schedulingCosts[task]), addedWeights, core);
+      Cost schedulingLoad = checkedAdd(
+        loads[core], schedulingCosts[task]);
+      Time transferTime = 0;
+      size_t candidateCpu = range.begin + core;
+      for (const auto &[predecessor, transferCost] :
+           graph.predecessors[task])
+        if (taskCpus[predecessor] < target.processorCount)
+          transferTime = checkedAdd(
+            transferTime, getPeftTransferTime(
+                            transferCost, taskCpus[predecessor],
+                            candidateCpu, target));
+      PackScore score {
+        assemblyLoad, transferTime, schedulingLoad, addedWeights, core};
       if (!bestScore || score < *bestScore) {
         bestCore = core;
         bestScore = score;
       }
     }
     if (!bestCore)
-      return;
+      return false;
     packed[*bestCore].push_back(task);
     insertResidentWeights(
       weights[*bestCore], graph.nodes[task].residentWeights);
     loads[*bestCore] = checkedAdd(loads[*bestCore], schedulingCosts[task]);
     assemblyLoads[*bestCore] = checkedAdd(
       assemblyLoads[*bestCore], assemblyCosts[task]);
+    taskCpus[task] = range.begin + *bestCore;
   }
-  if (*std::max_element(loads.begin(), loads.end()) > originalMaximum)
+  for (size_t core = 0; core < range.size; ++core)
-    return;
+    tasksByCpu[range.begin + core] = std::move(packed[core]);
-  for (size_t core = 0; core < groupSize; ++core)
+  return true;
-    tasksByCpu[stage * groupSize + core] = std::move(packed[core]);
 }
 
-static void rebalancePipelineStages(
+static LogicalResult packPipelineStages(
     const ComputeGraph &graph, const PipelineTaskModel &model,
-    std::vector<TaskList> &tasksByCpu, size_t groupSize,
+    std::vector<TaskList> &tasksByCpu, const PipelineCoreLayout &layout,
-    size_t pipelineStages, size_t residentWeightCapacity) {
+    size_t pipelineStages, size_t residentWeightCapacity,
-  size_t minimumAssemblyFanIn = std::numeric_limits<size_t>::max();
+    const SchedulingTarget &target, size_t &failedStage,
+    std::string &error) {
+  std::vector<size_t> indegree(graph.nodes.size());
+  std::vector<TaskList> successors(graph.nodes.size());
   for (size_t task = 0; task < graph.nodes.size(); ++task)
-    if (graph.nodes[task].instance.op && model.assemblyCosts[task] > 1
+    for (size_t predecessor : model.predecessors[task]) {
-        && !model.predecessors[task].empty())
+      successors[predecessor].push_back(task);
-      minimumAssemblyFanIn = std::min(
+      ++indegree[task];
-        minimumAssemblyFanIn, model.predecessors[task].size());
+    }
-  bool hasAssembly = minimumAssemblyFanIn != std::numeric_limits<size_t>::max();
+  auto laterOriginalOrder = [&](size_t lhs, size_t rhs) {
-  if (hasAssembly && groupSize < minimumAssemblyFanIn)
+    return graph.nodes[lhs].originalOrder > graph.nodes[rhs].originalOrder;
-    return;
-  const TaskCosts &balanceCosts =
-    hasAssembly ? model.assemblyCosts : model.schedulingCosts;
-
-  Cost schedulingLimit = 0;
-  for (const TaskList &tasks : tasksByCpu)
-    schedulingLimit = std::max(
-      schedulingLimit, getCoreCost(tasks, model.schedulingCosts));
-  for (size_t stage = 0; stage < pipelineStages; ++stage)
-    repackPipelineStage(
-      graph, model.schedulingCosts, balanceCosts, tasksByCpu,
-      groupSize, stage,
-      residentWeightCapacity);
-
-  std::vector<size_t> taskToCpu(graph.nodes.size());
-  for (size_t cpu = 0; cpu < tasksByCpu.size(); ++cpu)
-    for (size_t task : tasksByCpu[cpu])
-      taskToCpu[task] = cpu;
-
-  bool changed;
-  do {
-    changed = false;
-    for (size_t sourceStage = pipelineStages; sourceStage-- > 1;) {
-      size_t targetStage = sourceStage - 1;
-      while (true) {
-        Cost sourceMaximum = getStageMaximumAssemblyCost(
-          tasksByCpu, balanceCosts, groupSize, sourceStage);
-        Cost targetMaximum = getStageMaximumAssemblyCost(
-          tasksByCpu, balanceCosts, groupSize, targetStage);
-        if (targetMaximum >= sourceMaximum)
-          break;
-
-        struct Move {
-          size_t sourceCpu;
-          size_t targetCpu;
-          size_t task;
   };
-        std::optional<Move> best;
+  std::priority_queue<size_t, std::vector<size_t>, decltype(laterOriginalOrder)>
-        std::optional<std::tuple<size_t, Cost, Cost, size_t>> bestScore;
+    ready(laterOriginalOrder);
-        for (size_t sourceCpu = sourceStage * groupSize;
+  for (size_t task = 0; task < graph.nodes.size(); ++task)
-             sourceCpu < (sourceStage + 1) * groupSize; ++sourceCpu) {
+    if (indegree[task] == 0)
-          if (tasksByCpu[sourceCpu].empty())
+      ready.push(task);
-            continue;
+  std::vector<size_t> topologicalPosition(graph.nodes.size());
-          size_t task = tasksByCpu[sourceCpu].front();
+  size_t position = 0;
-          bool dependenciesReady = llvm::all_of(
+  while (!ready.empty()) {
-            model.predecessors[task], [&](size_t predecessor) {
+    size_t task = ready.top();
-              return taskToCpu[predecessor] / groupSize <= targetStage;
+    ready.pop();
-            });
+    topologicalPosition[task] = position++;
-          if (!dependenciesReady)
+    for (size_t successor : successors[task])
-            continue;
+      if (--indegree[successor] == 0)
+        ready.push(successor);
+  }
+  if (position != graph.nodes.size()) {
+    error = "pipeline rebalancing received a cyclic task graph";
+    return failure();
+  }
 
-          Cost sourceAfter = getCoreCost(
+  const TaskCosts &balanceCosts = getPipelineBalanceCosts(graph, model);
-            tasksByCpu[sourceCpu], balanceCosts)
+  std::vector<size_t> taskCpus(graph.nodes.size(), target.processorCount);
-                           - balanceCosts[task];
+  for (size_t stage = 0; stage < pipelineStages; ++stage)
-          for (size_t targetCpu = targetStage * groupSize;
+    if (!packPipelineStage(
-               targetCpu < (targetStage + 1) * groupSize; ++targetCpu) {
+          graph, model.schedulingCosts, balanceCosts, tasksByCpu,
-            const TaskList &targetTasks = tasksByCpu[targetCpu];
+          layout, topologicalPosition, stage, residentWeightCapacity,
-            if (!fitsResidentWeights(
+          target, taskCpus)) {
-                     graph, targetTasks, task, residentWeightCapacity))
+      failedStage = stage;
+      error = "pipeline scheduling cannot pack dependency-monotone stage "
+            + std::to_string(stage)
+            + " within the physical crossbar limit";
+      return failure();
+    }
+  return success();
+}
+
+static LogicalResult verifyPipelineStageAssignment(
+    const ComputeGraph &graph, const PipelineTaskModel &model,
+    const std::vector<TaskList> &tasksByCpu,
+    const PipelineCoreLayout &layout, std::string &error) {
+  const size_t noStage = std::numeric_limits<size_t>::max();
+  std::vector<size_t> taskStages(graph.nodes.size(), noStage);
+  llvm::DenseMap<Operation *, size_t> operationStages;
+  llvm::DenseMap<Attribute, size_t> splitOperationStages;
+  for (size_t cpu = 0; cpu < tasksByCpu.size(); ++cpu) {
+    std::optional<size_t> stage = layout.getStageForCore(cpu);
+    if (!stage) {
+      error = "pipeline scheduling assigned a task outside the stage layout";
+      return failure();
+    }
+    for (size_t task : tasksByCpu[cpu]) {
+      if (task >= graph.nodes.size() || taskStages[task] != noStage) {
+        error = "pipeline scheduling did not assign every task exactly once";
+        return failure();
+      }
+      taskStages[task] = *stage;
+      if (*stage != 0 && consumesPipelineInput(graph.nodes[task])) {
+        error = "pipeline scheduling assigned a direct function-input "
+                "consumer after stage zero";
+        return failure();
+      }
+      Operation *operation = graph.nodes[task].instance.op;
+      if (!operation)
         continue;
-            Cost targetAfter = checkedAdd(
+      Attribute splitGroup = operation->getAttr("pipeline.stage_group");
-              getCoreCost(targetTasks, balanceCosts), balanceCosts[task]);
+      bool consistent;
-            Cost targetSchedulingAfter = checkedAdd(
+      if (splitGroup) {
-              getCoreCost(targetTasks, model.schedulingCosts),
+        auto [entry, inserted] =
-              model.schedulingCosts[task]);
+          splitOperationStages.try_emplace(splitGroup, *stage);
-            if (targetAfter >= sourceMaximum
+        consistent = inserted || entry->second == *stage;
-                || targetSchedulingAfter > schedulingLimit)
+      } else {
-              continue;
+        auto [entry, inserted] =
-            auto score = std::make_tuple(
+          operationStages.try_emplace(operation, *stage);
-              graph.nodes[task].originalOrder,
+        consistent = inserted || entry->second == *stage;
-              std::max(sourceAfter, targetAfter), targetAfter, targetCpu);
+      }
-            if (!bestScore || score < *bestScore) {
+      if (!consistent) {
-              best = Move {sourceCpu, targetCpu, task};
+        error = "pipeline scheduling split one operation across stages";
-              bestScore = score;
+        return failure();
       }
     }
   }
-        if (!best)
+  if (llvm::is_contained(taskStages, noStage)) {
-          break;
+    error = "pipeline scheduling did not assign every task exactly once";
-        tasksByCpu[best->sourceCpu].erase(
+    return failure();
-          tasksByCpu[best->sourceCpu].begin());
-        TaskList &targetTasks = tasksByCpu[best->targetCpu];
-        auto insertion = llvm::find_if(targetTasks, [&](size_t task) {
-          return graph.nodes[task].originalOrder
-               > graph.nodes[best->task].originalOrder;
-        });
-        targetTasks.insert(insertion, best->task);
-        taskToCpu[best->task] = best->targetCpu;
-        changed = true;
   }
+  for (size_t task = 0; task < graph.nodes.size(); ++task)
+    for (size_t predecessor : model.predecessors[task])
+      if (taskStages[predecessor] > taskStages[task]
+          || taskStages[task] - taskStages[predecessor] > 1) {
+        error = "pipeline scheduling produced a backward or skipped-stage dependency";
+        return failure();
       }
-  } while (changed);
+  return success();
 }
 
 mlir::LogicalResult assignPipelineCores(const ComputeGraph& graph,
@@ -914,7 +1313,13 @@ mlir::LogicalResult assignPipelineCores(const ComputeGraph& graph,
                                         const SchedulingTarget& physicalTarget,
                                         std::string& error) {
   const size_t groupSize = schedule.processorCount;
-  std::vector<TaskList> tasksByCpu(groupSize);
+  PipelineCoreLayout balancedLayout(
+    physicalTarget.processorCount, pipelineStages);
+  if (!balancedLayout.isValid()
+      || groupSize != balancedLayout.getLogicalProcessorCount()) {
+    error = "pipeline scheduling received an incompatible physical core layout";
+    return mlir::failure();
+  }
   for (size_t task = 0; task < graph.nodes.size(); ++task) {
     const ComputeInstance& instance = graph.nodes[task].instance;
     auto cpu = schedule.computeToCpuMap.find(instance);
@@ -924,74 +1329,69 @@ mlir::LogicalResult assignPipelineCores(const ComputeGraph& graph,
       error = "pipeline scheduling received an incomplete PEFT schedule";
       return mlir::failure();
     }
-    tasksByCpu[cpu->second].push_back(task);
   }
-  for (TaskList& tasks : tasksByCpu)
-    llvm::sort(tasks, [&](size_t lhs, size_t rhs) {
-      return schedule.computeToCpuSlotMap.lookup(graph.nodes[lhs].instance)
-           < schedule.computeToCpuSlotMap.lookup(graph.nodes[rhs].instance);
-    });
   PipelineTaskModel taskModel = getPipelineTaskModel(
     graph, schedule, physicalTarget);
-  const TaskCosts &taskCosts = taskModel.schedulingCosts;
+  FailureOr<PipelineStageAssignment> assignment = assignPipelineStages(
-
+    graph, taskModel, balancedLayout,
+    physicalTarget.residentWeightCapacity, error);
+  if (failed(assignment))
+    return failure();
   std::vector<TaskList> tasksByPhysicalCpu(physicalTarget.processorCount);
-  for (size_t sourceCpu = 0; sourceCpu < groupSize; ++sourceCpu) {
+  std::vector<size_t> minimumPackableStageSizes(pipelineStages, 1);
-    const TaskList& tasks = tasksByCpu[sourceCpu];
+  std::string packingError;
-    if (tasks.empty())
+  bool packed = false;
-      continue;
+  for (size_t attempt = 0; attempt < physicalTarget.processorCount; ++attempt) {
-    for (size_t task : tasks)
+    PipelineCoreLayout candidateLayout(assignment->stageSizes);
-      if (graph.nodes[task].residentWeights.size() > physicalTarget.residentWeightCapacity) {
+    for (TaskList &tasks : tasksByPhysicalCpu)
-        error = "pipeline scheduling cannot fit one compute instance in a physical core's crossbars";
+      tasks.clear();
-        return mlir::failure();
+    for (size_t task = 0; task < graph.nodes.size(); ++task) {
+      PipelineStageRange range =
+        candidateLayout.getStageRange(assignment->taskStages[task]);
+      tasksByPhysicalCpu[range.begin].push_back(task);
     }
-
+    size_t failedStage = 0;
-    Cost maximumCost = findMaximumPackCost(
+    if (succeeded(packPipelineStages(
-      graph, taskCosts, tasks, physicalTarget.residentWeightCapacity, pipelineStages);
+          graph, taskModel, tasksByPhysicalCpu, candidateLayout,
-    if (!fits(graph, taskCosts, tasks, maximumCost,
+          pipelineStages, physicalTarget.residentWeightCapacity,
-              physicalTarget.residentWeightCapacity, pipelineStages)) {
+          physicalTarget, failedStage, packingError))) {
-      error = "pipeline scheduling cannot partition one PEFT core within the physical crossbar limit";
+      packed = true;
-      return mlir::failure();
+      break;
     }
-
+    minimumPackableStageSizes[failedStage] = std::max(
-    const size_t desiredPacks = std::min(pipelineStages, tasks.size());
+      minimumPackableStageSizes[failedStage],
-    size_t stage = 0;
+      assignment->stageSizes[failedStage] + 1);
-    Cost packCost = 0;
+    std::optional<size_t> donor;
-    ResidentWeightSet packWeights;
+    for (size_t stage = 0; stage < pipelineStages; ++stage)
-    bool packEmpty = true;
+      if (stage != failedStage
-    for (size_t index = 0; index < tasks.size(); ++index) {
+          && assignment->stageSizes[stage]
-      size_t task = tasks[index];
+               > minimumPackableStageSizes[stage]
-      const ComputeGraphNode& node = graph.nodes[task];
+          && (!donor
-      Cost taskCost = taskCosts[task];
+              || assignment->stageSizes[stage]
-      bool exceedsLimit =
+                   > assignment->stageSizes[*donor]))
-        !packEmpty
+        donor = stage;
-        && (packCost > maximumCost - taskCost
+    if (!donor)
-            || getResidentWeightUnionSize(packWeights, node.residentWeights) > physicalTarget.residentWeightCapacity);
+      break;
-      bool reserveOneTaskPerPack = !packEmpty && tasks.size() - index == desiredPacks - stage - 1;
+    --assignment->stageSizes[*donor];
-      if (exceedsLimit || reserveOneTaskPerPack) {
+    ++assignment->stageSizes[failedStage];
-        ++stage;
-        packCost = 0;
-        packWeights.clear();
-        packEmpty = true;
   }
-      if (stage >= pipelineStages) {
+  if (!packed) {
-        error = "pipeline scheduling produced too many packs";
+    error = packingError;
-        return mlir::failure();
+    return failure();
   }
-      size_t physicalCpu = sourceCpu + stage * groupSize;
+  PipelineCoreLayout pipelineLayout(assignment->stageSizes);
-      tasksByPhysicalCpu[physicalCpu].push_back(task);
+  if (failed(verifyPipelineStageAssignment(
-      packCost = checkedAdd(packCost, taskCost);
+        graph, taskModel, tasksByPhysicalCpu, pipelineLayout, error)))
-      insertResidentWeights(packWeights, node.residentWeights);
+    return failure();
-      packEmpty = false;
-    }
-  }
-
-  rebalancePipelineStages(
-    graph, taskModel, tasksByPhysicalCpu, groupSize, pipelineStages,
-    physicalTarget.residentWeightCapacity);
 
   schedule.computeToCpuMap.clear();
   schedule.processorCount = physicalTarget.processorCount;
+  schedule.processorStages.resize(physicalTarget.processorCount);
+  for (size_t stage = 0; stage < pipelineLayout.getStageCount(); ++stage) {
+    PipelineStageRange range = pipelineLayout.getStageRange(stage);
+    std::fill_n(
+      schedule.processorStages.begin() + range.begin, range.size, stage);
+  }
   schedule.computeToCpuSlotMap.clear();
   schedule.computeToAestMap.clear();
   schedule.isLastComputeOfCpu.clear();
@@ -1071,21 +1471,22 @@ mlir::LogicalResult applyPipelineScheduling(const ComputeGraph& graph,
                                             std::string& error) {
   if (pipelineStages == 1)
     return mlir::success();
-  if (pipelineStages == 0 || schedule.processorCount == 0
+  PipelineCoreLayout pipelineLayout(
-      || schedule.processorCount > std::numeric_limits<size_t>::max() / pipelineStages
+    physicalTarget.processorCount, pipelineStages);
-      || schedule.processorCount * pipelineStages != physicalTarget.processorCount) {
+  if (!pipelineLayout.isValid() || schedule.processorCount == 0
-    error = "pipeline scheduling requires physical cores = scheduled cores * pipeline stages";
+      || schedule.processorCount
+           != pipelineLayout.getLogicalProcessorCount()) {
+    error = "pipeline scheduling requires a valid balanced physical core layout";
     return mlir::failure();
   }
   return assignPipelineCores(graph, schedule, pipelineStages, physicalTarget, error);
 }
 
-mlir::LogicalResult splitPipelineWorkload(const ComputeGraph &graph,
+mlir::FailureOr<PipelineWorkloadPreparation> preparePipelineWorkload(
-                                          const MergeScheduleResult &schedule,
+    const ComputeGraph &graph, const MergeScheduleResult &schedule,
-                                          size_t pipelineStages,
+    size_t pipelineStages, const SchedulingTarget &physicalTarget,
-                                          const SchedulingTarget &physicalTarget,
     std::string &error) {
-  return splitPipelineWorkloadImpl(
+  return preparePipelineWorkloadImpl(
     graph, schedule, pipelineStages, physicalTarget, error);
 }
 

src/PIM/Dialect/Spatial/Passes/Transforms/MergeComputeNodes/Scheduling/PipelineScheduling.hpp

@@ -2,8 +2,15 @@
 
 #include "mlir/Support/LogicalResult.h"
 
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLExtras.h"
+
+#include <algorithm>
 #include <cstddef>
+#include <numeric>
+#include <optional>
 #include <string>
+#include <vector>
 
 #include "ComputeGraph.hpp"
 #include "MergeSchedule.hpp"
@@ -11,16 +18,82 @@
 
 namespace onnx_mlir::spatial {
 
+struct PipelineStageRange {
+  size_t begin;
+  size_t size;
+};
+
+class PipelineCoreLayout {
+public:
+  PipelineCoreLayout(size_t processorCount, size_t stageCount)
+      : processorCount(processorCount), stageSizes(stageCount) {
+    if (stageCount == 0)
+      return;
+    size_t baseSize = processorCount / stageCount;
+    size_t largerStageCount = processorCount % stageCount;
+    for (size_t stage = 0; stage < stageCount; ++stage)
+      stageSizes[stage] = baseSize + (stage < largerStageCount);
+  }
+
+  explicit PipelineCoreLayout(llvm::ArrayRef<size_t> stageSizes)
+      : processorCount(std::accumulate(
+          stageSizes.begin(), stageSizes.end(), size_t {0})),
+        stageSizes(stageSizes.begin(), stageSizes.end()) {}
+
+  bool isValid() const {
+    return !stageSizes.empty()
+        && llvm::none_of(stageSizes, [](size_t size) { return size == 0; });
+  }
+
+  size_t getLogicalProcessorCount() const {
+    return isValid()
+      ? *std::min_element(stageSizes.begin(), stageSizes.end())
+      : 0;
+  }
+
+  size_t getStageCount() const { return stageSizes.size(); }
+
+  size_t getProcessorCount() const { return processorCount; }
+
+  llvm::ArrayRef<size_t> getStageSizes() const { return stageSizes; }
+
+  PipelineStageRange getStageRange(size_t stage) const {
+    return {std::accumulate(
+              stageSizes.begin(), stageSizes.begin() + stage, size_t {0}),
+            stageSizes[stage]};
+  }
+
+  std::optional<size_t> getStageForCore(size_t core) const {
+    if (!isValid() || core >= processorCount)
+      return std::nullopt;
+    size_t end = 0;
+    for (auto [stage, size] : llvm::enumerate(stageSizes)) {
+      end += size;
+      if (core < end)
+        return stage;
+    }
+    return std::nullopt;
+  }
+
+private:
+  size_t processorCount;
+  std::vector<size_t> stageSizes;
+};
+
 mlir::LogicalResult applyPipelineScheduling(const ComputeGraph& graph,
                                             MergeScheduleResult& schedule,
                                             size_t pipelineStages,
                                             const SchedulingTarget& physicalTarget,
                                             std::string& error);
 
-mlir::LogicalResult splitPipelineWorkload(const ComputeGraph& graph,
+enum class PipelineWorkloadPreparation {
-                                          const MergeScheduleResult& schedule,
+  Ready,
-                                          size_t pipelineStages,
+  Changed,
-                                          const SchedulingTarget& physicalTarget,
+};
+
+mlir::FailureOr<PipelineWorkloadPreparation> preparePipelineWorkload(
+    const ComputeGraph& graph, const MergeScheduleResult& schedule,
+    size_t pipelineStages, const SchedulingTarget& physicalTarget,
     std::string& error);
 
 } // namespace onnx_mlir::spatial

test/PIM/SpatialSchedulingTargetTest.cpp

@@ -9,6 +9,36 @@
 using namespace onnx_mlir::spatial;
 
 int main() {
+  PipelineCoreLayout unevenLayout(138, 4);
+  assert(unevenLayout.isValid());
+  assert(unevenLayout.getLogicalProcessorCount() == 34);
+  assert(unevenLayout.getStageRange(0).begin == 0);
+  assert(unevenLayout.getStageRange(0).size == 35);
+  assert(unevenLayout.getStageRange(1).begin == 35);
+  assert(unevenLayout.getStageRange(1).size == 35);
+  assert(unevenLayout.getStageRange(2).begin == 70);
+  assert(unevenLayout.getStageRange(2).size == 34);
+  assert(unevenLayout.getStageRange(3).begin == 104);
+  assert(unevenLayout.getStageRange(3).size == 34);
+  assert(unevenLayout.getStageForCore(34) == 0);
+  assert(unevenLayout.getStageForCore(35) == 1);
+  assert(unevenLayout.getStageForCore(69) == 1);
+  assert(unevenLayout.getStageForCore(70) == 2);
+  assert(unevenLayout.getStageForCore(137) == 3);
+  assert(!unevenLayout.getStageForCore(138));
+
+  PipelineCoreLayout dynamicLayout(std::vector<size_t> {2, 4, 1, 3});
+  assert(dynamicLayout.isValid());
+  assert(dynamicLayout.getProcessorCount() == 10);
+  assert(dynamicLayout.getStageRange(0).begin == 0);
+  assert(dynamicLayout.getStageRange(1).begin == 2);
+  assert(dynamicLayout.getStageRange(2).begin == 6);
+  assert(dynamicLayout.getStageRange(3).begin == 7);
+  assert(dynamicLayout.getStageForCore(1) == 0);
+  assert(dynamicLayout.getStageForCore(2) == 1);
+  assert(dynamicLayout.getStageForCore(6) == 2);
+  assert(dynamicLayout.getStageForCore(9) == 3);
+
   TransferCost transfer {.fixed = 50, .networkFlits = 4};
 
   SchedulingTarget fast;
@@ -57,6 +87,13 @@ int main() {
   };
   assert(mapLogicalProcessorsToPhysicalCores(logicalTrafficFlits, alreadyPlaced) == std::vector<size_t>({0, 1, 2}));
 
+  std::vector<size_t> placementGroups {0, 1, 1};
+  std::vector<size_t> groupedPlacement = mapLogicalProcessorsToPhysicalCores(
+    logicalTrafficFlits, line, placementGroups);
+  for (size_t processor = 0; processor < groupedPlacement.size(); ++processor)
+    assert(placementGroups[processor]
+           == placementGroups[groupedPlacement[processor]]);
+
   ComputeGraph graph;
   graph.successors.resize(6);
   graph.predecessors.resize(6);
@@ -71,16 +108,16 @@ int main() {
     graph.instanceToIndex[instance] = task;
   }
 
-  MergeScheduleResult pipelineSchedule;
+  MergeScheduleResult logicalSchedule;
-  pipelineSchedule.processorCount = 2;
+  logicalSchedule.processorCount = 2;
-  pipelineSchedule.dominanceOrderCompute.reserve(graph.nodes.size());
+  logicalSchedule.dominanceOrderCompute.reserve(graph.nodes.size());
   for (size_t task = 0; task < graph.nodes.size(); ++task) {
     const ComputeInstance& instance = graph.nodes[task].instance;
-    pipelineSchedule.dominanceOrderCompute.push_back(instance);
+    logicalSchedule.dominanceOrderCompute.push_back(instance);
     size_t cpu = task < 4 ? 0 : 1;
-    pipelineSchedule.computeToCpuMap[instance] = cpu;
+    logicalSchedule.computeToCpuMap[instance] = cpu;
-    pipelineSchedule.computeToCpuSlotMap[instance] = task < 4 ? task : task - 4;
+    logicalSchedule.computeToCpuSlotMap[instance] = task < 4 ? task : task - 4;
-    pipelineSchedule.computeToAestMap[instance] = task;
+    logicalSchedule.computeToAestMap[instance] = task;
   }
 
   SchedulingTarget physical = fast;
@@ -93,20 +130,50 @@ int main() {
     3, 3, 3, 0,
   };
   std::string pipelineError;
+  MergeScheduleResult pipelineSchedule = logicalSchedule;
   assert(mlir::succeeded(applyPipelineScheduling(
     graph, pipelineSchedule, 2, physical, pipelineError)));
   assert(pipelineSchedule.processorCount == 4);
-  assert(pipelineSchedule.computeToCpuMap.lookup(graph.nodes[0].instance) == 0);
+  size_t predecessorCore = pipelineSchedule.computeToCpuMap.lookup(
-  assert(pipelineSchedule.computeToCpuMap.lookup(graph.nodes[1].instance) == 0);
+    graph.nodes[1].instance);
-  assert(pipelineSchedule.computeToCpuMap.lookup(graph.nodes[2].instance) == 2);
+  size_t successorCore = pipelineSchedule.computeToCpuMap.lookup(
-  assert(pipelineSchedule.computeToCpuMap.lookup(graph.nodes[3].instance) == 2);
+    graph.nodes[2].instance);
-  assert(pipelineSchedule.computeToCpuMap.lookup(graph.nodes[4].instance) == 1);
-  assert(pipelineSchedule.computeToCpuMap.lookup(graph.nodes[5].instance) == 3);
   assert(pipelineSchedule.computeToAestMap.lookup(graph.nodes[2].instance)
          >= pipelineSchedule.computeToAestMap.lookup(graph.nodes[1].instance)
-              + graph.nodes[1].cost + 4);
+              + graph.nodes[1].cost
+              + getPeftTransferTime(
+                  TransferCost {.fixed = 1, .networkFlits = 1},
+                  predecessorCore, successorCore, physical));
+  assert(pipelineSchedule.processorStages[predecessorCore]
+         <= pipelineSchedule.processorStages[successorCore]);
+  assert(pipelineSchedule.processorStages[successorCore]
+         <= pipelineSchedule.processorStages[predecessorCore] + 1);
   assert(pipelineSchedule.equivalentClass.empty());
 
+  graph.successors[0].push_back(
+    {5, TransferCost {.fixed = 1, .networkFlits = 1}});
+  graph.predecessors[5].push_back(
+    {0, TransferCost {.fixed = 1, .networkFlits = 1}});
+  SchedulingTarget fourStagePhysical = physical;
+  fourStagePhysical.processorCount = 8;
+  fourStagePhysical.interProcessorLatencyNs.assign(64, 3);
+  for (size_t core = 0; core < 8; ++core)
+    fourStagePhysical.interProcessorLatencyNs[core * 8 + core] = 0;
+  MergeScheduleResult fourStageSchedule = logicalSchedule;
+  assert(mlir::succeeded(applyPipelineScheduling(
+    graph, fourStageSchedule, 4, fourStagePhysical, pipelineError)));
+  for (size_t task = 0; task < graph.nodes.size(); ++task)
+    for (const auto &[predecessor, cost] : graph.predecessors[task]) {
+      (void)cost;
+      size_t sourceStage = fourStageSchedule.processorStages[
+        fourStageSchedule.computeToCpuMap.lookup(
+          graph.nodes[predecessor].instance)];
+      size_t targetStage = fourStageSchedule.processorStages[
+        fourStageSchedule.computeToCpuMap.lookup(graph.nodes[task].instance)];
+      assert(sourceStage <= targetStage);
+      assert(targetStage <= sourceStage + 1);
+    }
+
   ComputeGraph communicationGraph;
   communicationGraph.successors.resize(5);
   communicationGraph.predecessors.resize(5);
@@ -136,15 +203,19 @@ int main() {
   MergeScheduleResult fastCommunicationSchedule = communicationSchedule;
   assert(mlir::succeeded(applyPipelineScheduling(
     communicationGraph, fastCommunicationSchedule, 2, fastPipeline, pipelineError)));
-  assert(fastCommunicationSchedule.computeToCpuMap.lookup(
-           communicationGraph.nodes[2].instance) == 2);
 
   SchedulingTarget slowPipeline = fastPipeline;
   slowPipeline.averageInterProcessorLatencyNs = 10;
   MergeScheduleResult slowCommunicationSchedule = communicationSchedule;
   assert(mlir::succeeded(applyPipelineScheduling(
     communicationGraph, slowCommunicationSchedule, 2, slowPipeline, pipelineError)));
-  assert(slowCommunicationSchedule.computeToCpuMap.lookup(
+  size_t sourceCore = slowCommunicationSchedule.computeToCpuMap.lookup(
-           communicationGraph.nodes[2].instance) < 2);
+    communicationGraph.nodes[4].instance);
+  size_t targetCore = slowCommunicationSchedule.computeToCpuMap.lookup(
+    communicationGraph.nodes[3].instance);
+  assert(slowCommunicationSchedule.processorStages[sourceCore]
+         <= slowCommunicationSchedule.processorStages[targetCore]);
+  assert(slowCommunicationSchedule.processorStages[targetCore]
+         <= slowCommunicationSchedule.processorStages[sourceCore] + 1);
   return EXIT_SUCCESS;
 }

validation/.gitignore

@@ -9,6 +9,7 @@ operations/**/*.csv
 networks/**/inputs
 networks/**/outputs
 networks/**/raptor
+networks/**/raptor_functional
 networks/**/pimcomp
 networks/**/runner
 networks/**/simulation

validation/networks/pimcomp_models/results.csv

@@ -1,41 +1,61 @@
-model,arch,mode,raptor_pipeline,pimcomp_pipeline,raptor_functional_validation,pimcomp_functional_validation,raptor_throughput_samples_s,pimcomp_throughput_samples_s,raptor_latency_ms,pimcomp_latency_ms,raptor_power_mw,pimcomp_power_mw,raptor_energy_pj,pimcomp_energy_pj,better_compiler,speedup
+arch,model,mode,raptor_pipeline,pimcomp_pipeline,raptor_functional_validation,pimcomp_functional_validation,raptor_latency_ms,pimcomp_latency_ms,raptor_throughput_samples_s,pimcomp_throughput_samples_s,raptor_power_mw,pimcomp_power_mw,raptor_energy_pj,pimcomp_energy_pj,better_compiler,speedup
-vgg8,arch-a,latency,1,element,PASS,PASS,NA,NA,1.465778,7.985074,325.627854,200.111367,477298145.040001,1597904071.120000,raptor,5.45
+arch-a,vgg8,latency,1,element,PASS,PASS,1.47,7.99,NA,NA,325.67,200.11,477232782.04,1597904071.12,raptor,5.45
-vgg8,arch-b,latency,1,element,PASS,PASS,NA,NA,1.438869,7.152125,304.673458,173.768633,438385194.040001,1242814988.120001,raptor,4.97
+arch-a,vgg8,throughput,2,batch,PASS,PASS,0.94,1.04,1060.00,965.00,377.54,482.60,474325940.70,541691691.00,raptor,1.10
-vgg8,arch-c,latency,1,element,FAIL,PASS,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA
+arch-a,vgg8,throughput,4,batch,PASS,PASS,1.19,1.04,839.00,965.00,310.32,482.60,500148858.20,541691691.00,pimcomp,1.15
-vgg8,arch-a,throughput,2,batch,PASS,PASS,1480.000000,1380.000000,0.674197,0.725548,456.064662,475.694103,307477506.200000,345138738.300000,raptor,1.07
+arch-a,vgg8,throughput,8,batch,PASS,PASS,1.52,1.04,658.00,965.00,279.37,482.60,554348483.90,541691691.00,pimcomp,1.47
-vgg8,arch-b,throughput,2,batch,PASS,PASS,1160.000000,1080.000000,0.861527,0.921878,333.045167,408.540967,286927542.600000,376624916.800000,raptor,1.07
+arch-a,resnet18,latency,1,element,PASS,FAIL,15.65,58.18,NA,NA,425.87,238.39,6666000553.12,13869146503.12,raptor,3.72
-vgg8,arch-c,throughput,2,batch,FAIL,PASS,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA
+arch-a,resnet18,throughput,2,batch,PASS,FAIL,30.55,13.46,32.70,74.30,295.90,481.60,10218790630.00,6562535800.00,pimcomp,2.27
-vgg8,arch-a,throughput,4,batch,PASS,PASS,2160.000000,1380.000000,0.462342,0.725548,446.528150,475.694103,206448818.800000,345138738.300000,raptor,1.57
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validation/operations/validation_results.csv

@@ -1,178 +1,178 @@
 Operation,Arch,Result (l),Result (t),Compile (l),Host mem (l),Cores mem (l),Cores (l),Xbars (l),Latency (l),Power (l),Energy (l),Compile (t),Host mem (t),Cores mem (t),Cores (t),Xbars (t),Avg latency (t),Throughput (t),Avg power (t),Avg energy (t)
-add/after_gemm,arch-a,PASS,PASS,0.058 s,0.01 MiB,0.01 MiB,5,4,0.01 ms,104.70 mW,815012.96 pJ,0.057 s,0.01 MiB,0.01 MiB,6,4,145000.00 samples/s,0.01 ms,31.45 mW,216167.21 pJ/it
+add/after_gemm,arch-a,PASS,PASS,0.056 s,0.01 MiB,0.01 MiB,5,4,0.01 ms,104.70 mW,815012.96 pJ,0.043 s,0.01 MiB,0.01 MiB,6,4,218000.00 samples/s,0.00 ms,107.94 mW,570766.12 pJ/it
-add/basic,arch-a,PASS,PASS,0.048 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25266.00 pJ,0.050 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,658.67 pJ/it
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+slice/negative_indices,arch-a,PASS,PASS,0.052 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.30 mW,25212.00 pJ,0.037 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.30 mW,675.67 pJ/it
-slice/step2,arch-a,PASS,PASS,0.054 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.29 mW,159876.00 pJ,0.053 s,0.00 MiB,0.00 MiB,1,0,490000.00 samples/s,0.00 ms,2.29 mW,4619.67 pJ/it
+slice/step2,arch-a,PASS,PASS,0.053 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.29 mW,159876.00 pJ,0.042 s,0.00 MiB,0.00 MiB,1,0,490000.00 samples/s,0.00 ms,2.29 mW,4619.67 pJ/it
-softmax/3d_last_axis,arch-a,PASS,PASS,0.056 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.056 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
+softmax/3d_last_axis,arch-a,PASS,PASS,0.048 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.035 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
-softmax/basic,arch-a,PASS,PASS,0.062 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.058 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
+softmax/basic,arch-a,PASS,PASS,0.048 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.036 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
-softmax/channel_axis,arch-a,PASS,PASS,0.060 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.067 s,0.00 MiB,0.00 MiB,3,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
+softmax/channel_axis,arch-a,PASS,PASS,0.050 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.040 s,0.00 MiB,0.00 MiB,3,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
-softmax/large_dimension_1024,arch-a,PASS,PASS,0.059 s,0.01 MiB,0.01 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.054 s,0.01 MiB,0.01 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
+softmax/large_dimension_1024,arch-a,PASS,PASS,0.049 s,0.01 MiB,0.01 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.036 s,0.01 MiB,0.01 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
-softmax/negative_axis,arch-a,PASS,PASS,0.059 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.060 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
+softmax/negative_axis,arch-a,PASS,PASS,0.048 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,0.036 s,0.00 MiB,0.00 MiB,1,0,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED,UNSUPPORTED
-split/basic,arch-a,PASS,PASS,0.114 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.30 mW,31554.00 pJ,0.067 s,0.00 MiB,0.00 MiB,1,0,2490000.00 samples/s,0.00 ms,2.30 mW,861.67 pJ/it
+split/basic,arch-a,PASS,PASS,0.051 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.30 mW,31554.00 pJ,0.037 s,0.00 MiB,0.00 MiB,1,0,2490000.00 samples/s,0.00 ms,2.30 mW,861.67 pJ/it
-split/equal_three_way,arch-a,PASS,PASS,0.060 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.30 mW,44160.00 pJ,0.073 s,0.00 MiB,0.00 MiB,1,0,1780000.00 samples/s,0.00 ms,2.30 mW,1231.67 pJ/it
+split/equal_three_way,arch-a,PASS,PASS,0.049 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.30 mW,44160.00 pJ,0.035 s,0.00 MiB,0.00 MiB,1,0,1780000.00 samples/s,0.00 ms,2.30 mW,1231.67 pJ/it
-split/negative_axis,arch-a,PASS,PASS,0.061 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.29 mW,84786.00 pJ,0.059 s,0.00 MiB,0.00 MiB,1,0,925000.00 samples/s,0.00 ms,2.29 mW,2413.67 pJ/it
+split/negative_axis,arch-a,PASS,PASS,0.053 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.29 mW,84786.00 pJ,0.039 s,0.00 MiB,0.00 MiB,1,0,925000.00 samples/s,0.00 ms,2.29 mW,2413.67 pJ/it
-split/uneven_channel_axis_4d,arch-a,PASS,PASS,0.058 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.30 mW,18948.00 pJ,0.060 s,0.00 MiB,0.00 MiB,1,0,4170000.00 samples/s,0.00 ms,2.30 mW,491.67 pJ/it
+split/uneven_channel_axis_4d,arch-a,PASS,PASS,0.049 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.30 mW,18948.00 pJ,0.046 s,0.00 MiB,0.00 MiB,1,0,4170000.00 samples/s,0.00 ms,2.30 mW,491.67 pJ/it
-sub/after_gemm,arch-a,PASS,PASS,0.065 s,0.01 MiB,0.01 MiB,5,4,0.01 ms,104.70 mW,815012.96 pJ,0.065 s,0.01 MiB,0.01 MiB,6,4,145000.00 samples/s,0.01 ms,31.45 mW,216167.21 pJ/it
+sub/after_gemm,arch-a,PASS,PASS,0.056 s,0.01 MiB,0.01 MiB,5,4,0.01 ms,104.70 mW,815012.96 pJ,0.045 s,0.01 MiB,0.01 MiB,6,4,218000.00 samples/s,0.00 ms,107.94 mW,570766.12 pJ/it
-sub/basic,arch-a,PASS,PASS,0.062 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25266.00 pJ,0.055 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,658.67 pJ/it
+sub/basic,arch-a,PASS,PASS,0.046 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25266.00 pJ,0.037 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,658.67 pJ/it
-sub/broadcast_row,arch-a,PASS,PASS,0.059 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25266.00 pJ,0.077 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,658.67 pJ/it
+sub/broadcast_row,arch-a,PASS,PASS,0.049 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25266.00 pJ,0.042 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,658.67 pJ/it
-sub/channel_broadcast_1024,arch-a,PASS,PASS,0.064 s,0.02 MiB,0.01 MiB,1,0,0.01 ms,78.12 mW,540030.00 pJ,0.058 s,0.02 MiB,0.01 MiB,1,0,145000.00 samples/s,0.01 ms,2.11 mW,13388.67 pJ/it
+sub/channel_broadcast_1024,arch-a,PASS,PASS,0.052 s,0.02 MiB,0.01 MiB,1,0,0.01 ms,78.12 mW,540030.00 pJ,0.037 s,0.02 MiB,0.01 MiB,1,0,145000.00 samples/s,0.01 ms,2.11 mW,13388.67 pJ/it
-sub/constant_lhs_broadcast,arch-a,PASS,PASS,0.057 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25188.00 pJ,0.061 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,656.67 pJ/it
+sub/constant_lhs_broadcast,arch-a,PASS,PASS,0.049 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25188.00 pJ,0.034 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,656.67 pJ/it
-sub/leading_dimension_broadcast,arch-a,PASS,PASS,0.056 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25266.00 pJ,0.057 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,658.67 pJ/it
+sub/leading_dimension_broadcast,arch-a,PASS,PASS,0.050 s,0.00 MiB,0.00 MiB,1,0,0.00 ms,78.22 mW,25266.00 pJ,0.038 s,0.00 MiB,0.00 MiB,1,0,3120000.00 samples/s,0.00 ms,2.23 mW,658.67 pJ/it

validation/tools/pim/pimcomp/compare/compare_raptor_pimcomp.py

@@ -1153,6 +1153,7 @@ def write_report(
     pimcomp_pipeline: str,
     pimcomp_replication: str,
 ):
+    report_path.parent.mkdir(parents=True, exist_ok=True)
     lines = [
         "# Raptor vs PIMCOMP Comparison Report",
         "",
@@ -1302,6 +1303,11 @@ def write_report(
 def main():
     parser = argparse.ArgumentParser()
     parser.add_argument("--model", required=True, type=Path)
+    parser.add_argument(
+        "--functional-model",
+        type=Path,
+        help="Optional canonical model used only for Raptor functional validation.",
+    )
     parser.add_argument("--out-dir", required=True, type=Path)
     parser.add_argument(
         "--common-dir",
@@ -1325,7 +1331,7 @@ def main():
     parser.add_argument("--pimsim-nn-build-dir", default=REPO / "backend-simulators/pim/pimsim-nn/build", type=Path)
     parser.add_argument("--seed", type=int, default=0)
     parser.add_argument("--threshold", type=float, default=1e-3)
-    parser.add_argument("--rtol", type=float, default=1e-5)
+    parser.add_argument("--rtol", type=float, default=1e-4)
     parser.add_argument(
         "--timeout-seconds",
         type=float,
@@ -1390,6 +1396,11 @@ def main():
         args.pimcomp_pipeline = "element" if args.pimsim_mode == "latency" else "batch"
 
     model_path = args.model.resolve()
+    functional_model_path = (
+        args.functional_model.resolve()
+        if args.functional_model is not None
+        else model_path
+    )
     args.pimcomp_dir = args.pimcomp_dir.resolve()
     args.pimcomp_config = (
         args.pimcomp_config.resolve()
@@ -1407,7 +1418,7 @@ def main():
 
     if args.prepare_common:
         print_step("Prepare shared artifacts")
-        prepare_common_artifacts(args, model_path, common_dir)
+        prepare_common_artifacts(args, functional_model_path, common_dir)
         print(f"Shared artifacts: {common_dir}")
         return
 
@@ -1450,7 +1461,13 @@ def main():
     if loaded_hardware is not None:
         hardware = loaded_hardware
 
-    model_io = try_stage(failures, "Load model inputs", load_model_inputs, model_path, args.seed)
+    model_io = try_stage(
+        failures,
+        "Load model inputs",
+        load_model_inputs,
+        functional_model_path,
+        args.seed,
+    )
     if model_io is not None:
         inputs_desc, outputs_desc, arrays_in_order = model_io
         runtime_inputs = arrays_in_order
@@ -1530,7 +1547,7 @@ def main():
                 "Compile reference",
                 compile_reference,
                 args,
-                model_path,
+                functional_model_path,
                 common_dir,
                 steps,
             )
@@ -1548,7 +1565,7 @@ def main():
                     generate_reference_outputs,
                     runner_path,
                     runner_path.parent,
-                    model_path,
+                    functional_model_path,
                     arrays_in_order,
                     steps,
                     args,
@@ -1578,7 +1595,7 @@ def main():
                 generate_reference_batch_outputs,
                 runner_path,
                 runner_path.parent,
-                model_path,
+                functional_model_path,
                 input_batch,
                 steps,
                 args,
@@ -1610,13 +1627,33 @@ def main():
             "Raptor PIM compile was skipped because the ONNX model or hardware configuration is not available.",
         )
 
-    if not reuse_raptor and raptor_pim_dir is not None:
+    raptor_functional_pim_dir = raptor_pim_dir
+    if (
+        not reuse_raptor
+        and functional_model_path != model_path
+        and hardware["core_count"] > 0
+    ):
+        compiled_functional = try_stage(
+            failures,
+            "Compile Raptor functional PIM",
+            compile_raptor_target,
+            functional_model_path,
+            out_dir / "raptor_functional",
+            hardware,
+            args,
+            steps,
+        )
+        raptor_functional_pim_dir = (
+            compiled_functional[0] if compiled_functional is not None else None
+        )
+
+    if not reuse_raptor and raptor_functional_pim_dir is not None:
         wrote_inputs = try_stage_success(
             failures,
             "Write Raptor inputs",
             write_inputs_to_memory_bin,
-            raptor_pim_dir / "memory.bin",
+            raptor_functional_pim_dir / "memory.bin",
-            raptor_pim_dir / "config.json",
+            raptor_functional_pim_dir / "config.json",
             runtime_inputs,
         )
         if wrote_inputs and reference_dirs and outputs_desc:
@@ -1625,8 +1662,8 @@ def main():
                 "Functional Validation Raptor",
                 run_functional_validation,
                 "Functional Validation Raptor",
-                raptor_pim_dir,
+                raptor_functional_pim_dir,
-                raptor_pim_dir / "config.json",
+                raptor_functional_pim_dir / "config.json",
                 out_dir / "simulation/out.bin",
                 raptor_input_bins,
                 outputs_desc,
@@ -1847,6 +1884,7 @@ def main():
 
     json_report = {
         "model": str(model_path),
+        "functional_model": str(functional_model_path),
         "hardware": hardware,
         "pimsim_mode": args.pimsim_mode,
         "pimsim_time_ms": args.pimsim_time_ms,
@@ -1874,6 +1912,7 @@ def main():
             "batch_outputs": optional_path(out_dir / "simulation/out_iterations"),
             "reference_runner": optional_path(runner_path),
             "raptor_pim": optional_path(raptor_pim_dir),
+            "raptor_functional_pim": optional_path(raptor_functional_pim_dir),
             "raptor_pimsim_nn": optional_path(raptor_pimsim_dir),
             "pimcomp_simulation_info": optional_path(simulation_info),
             "pimcomp_exported_pim": optional_path(pimcomp_export_dir),

validation/tools/pim/pimcomp/compare/run_pimcomp_paper_latency.py

@@ -36,6 +36,10 @@ MODELS = {
     "googlenet": SUITE / "googlenet/googlenet-12-pimsim-nn.onnx",
     "yolo11n": SUITE / "yolo11n/yolo11n-pimsim-nn.onnx",
 }
+FUNCTIONAL_MODELS = {
+    **MODELS,
+    "yolo11n": REPO / "validation/networks/yolo11n/depth_51/yolo11n_depth_51.onnx",
+}
 COMPARISONS = (
     ("latency", 1, "element"),
     ("throughput", 2, "batch"),
@@ -48,6 +52,7 @@ COMPARISONS = (
 class ComparisonSpec:
     label: str
     model: Path
+    functional_model: Path
     output_dir: Path
     common_dir: Path
     config: Path
@@ -68,6 +73,11 @@ def result_dir(root: Path | None, name: str, arch: str, mode: str, pipeline: int
     return base / arch / suffix
 
 
+def common_dir(root: Path | None, name: str) -> Path:
+    suffix = "common" if FUNCTIONAL_MODELS[name] == MODELS[name] else "common-functional"
+    return model_dir(root, name) / suffix
+
+
 def clean_artifacts(root: Path | None, models: list[str], arches: list[str]) -> int:
     removed = 0
     for name in models:
@@ -78,7 +88,7 @@ def clean_artifacts(root: Path | None, models: list[str], arches: list[str]) ->
             if path.is_dir() and not path.is_symlink():
                 shutil.rmtree(path)
                 removed += 1
-        common = base / "common"
+        for common in (base / "common", base / "common-functional"):
             if common.is_dir() and not common.is_symlink():
                 shutil.rmtree(common)
                 removed += 1
@@ -316,6 +326,7 @@ def validate_pimcomp_source() -> None:
 
 def comparison_command(
     model: Path,
+    functional_model: Path,
     result_dir: Path,
     common_dir: Path,
     config: Path,
@@ -343,6 +354,8 @@ def comparison_command(
         str(COMPARE),
         "--model",
         str(model),
+        "--functional-model",
+        str(functional_model),
         "--out-dir",
         str(result_dir),
         "--common-dir",
@@ -394,6 +407,7 @@ def comparison_command_for(
     report = spec.output_dir / "pimcomp/comparison_report.json"
     return comparison_command(
         spec.model,
+        spec.functional_model,
         spec.output_dir,
         spec.common_dir,
         spec.config,
@@ -586,7 +600,12 @@ def main() -> int:
         comparisons_by_arch[arch] = comparisons
         configs_by_arch[arch] = configs
 
-    missing = [str(MODELS[name]) for name in args.models if not MODELS[name].exists()]
+    missing = [
+        str(path)
+        for name in args.models
+        for path in (MODELS[name], FUNCTIONAL_MODELS[name])
+        if not path.exists()
+    ]
     if missing:
         parser.error(f"missing model(s): {', '.join(missing)}")
 
@@ -631,8 +650,8 @@ def main() -> int:
         try:
             run(
                 prepare_common_command(
-                    MODELS[name],
+                    FUNCTIONAL_MODELS[name],
-                    model_dir(out_dir, name) / "common",
+                    common_dir(out_dir, name),
                     args.timeout_seconds,
                 ),
                 dry_run=args.dry_run,
@@ -660,8 +679,9 @@ def main() -> int:
                     ComparisonSpec(
                         label=label,
                         model=MODELS[name],
+                        functional_model=FUNCTIONAL_MODELS[name],
                         output_dir=model_result_dir,
-                        common_dir=model_dir(out_dir, name) / "common",
+                        common_dir=common_dir(out_dir, name),
                         config=configs[mode],
                         mode=mode,
                         pipeline=pipeline,