slightly faster codegen
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@@ -24,6 +24,10 @@
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namespace onnx_mlir {
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struct CompiledCoreProgram;
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struct CompiledTransposePlan;
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class PimInstructionWriter;
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struct MemEntry {
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size_t address;
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size_t size;
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@@ -35,9 +39,7 @@ struct PhysicalSlotInfo {
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size_t size = 0;
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};
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struct MemoryPlanArtifacts {
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std::string textReport;
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};
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using MemoryPlanArtifacts = std::string;
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struct MemoryValueKey {
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mlir::Value value;
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@@ -98,6 +100,7 @@ class PimMemory {
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size_t nextPhysicalSlotId = 0;
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MemEntry* gatherMemEntry(mlir::Value value, std::optional<unsigned> lane = std::nullopt);
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size_t allocateAddress(size_t size, const MemoryValueKey& key);
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void allocateGatheredMemory();
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void allocateMemoryForValue(const MemoryValueKey& key, MemEntry& memEntry, MemoryReportKind reportKind);
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PhysicalSlotInfo allocatePhysicalSlot(size_t slotSize, const MemoryValueKey& key);
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@@ -110,7 +113,6 @@ public:
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void allocateCore(mlir::Operation* op, std::optional<unsigned> lane = std::nullopt);
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MemoryReportRow getReportRow() const;
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const MemoryPlanArtifacts& getLivenessArtifacts() const { return livenessArtifacts; }
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void remove(mlir::Value val);
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size_t getFirstAvailableAddress() const { return firstAvailableAddress; }
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MemEntry getMemEntry(const MemoryValueKey& key) const;
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@@ -153,12 +155,11 @@ public:
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uint64_t totalAllocaBytes);
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void setTotalWeightBytes(uint64_t bytes) { totalWeightBytes = bytes; }
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void flushReport();
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void clean(mlir::Operation* op);
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};
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struct CoreEmissionJob {
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mlir::Operation* coreLikeOp = nullptr;
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size_t originalCoreId = 0;
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const CompiledCoreProgram* program = nullptr;
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size_t emittedCoreId = 0;
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llvm::SmallVector<unsigned, 4> lanes;
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std::optional<uint64_t> batchReportId;
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@@ -166,11 +167,10 @@ struct CoreEmissionJob {
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class PimCodeGen {
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PimAcceleratorMemory& memory;
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llvm::raw_fd_ostream& coreBinaryStream;
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PimInstructionWriter& instructionWriter;
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llvm::raw_fd_ostream* coreJsonStream;
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const llvm::DenseMap<size_t, size_t>& emittedCoreIds;
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std::optional<unsigned> batchLane;
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mutable uint32_t emittedInstructionCount = 0;
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mutable std::array<std::optional<int32_t>, 256> scalarRegisterValues = {};
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size_t addressOf(mlir::Value value, const StaticValueKnowledge& knowledge) const {
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@@ -181,30 +181,44 @@ class PimCodeGen {
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void emitInstruction(const pim_binary::InstructionRecord& instruction) const;
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void updateScalarRegisterCache(const pim_binary::InstructionRecord& instruction) const;
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void genSetRegisterImmediate(uint8_t registerNumber, int32_t immediate) const;
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void genSetRegisterImmediateUnsigned(size_t registerNumber, size_t immediate) const;
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void setupRd(size_t rdAddress, size_t rdOffset) const;
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void setupRdRs1(size_t rdAddress, size_t rdOffset, size_t rs1Address, size_t rs1Offset) const;
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void setupRdRs1Rs2(
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size_t rdAddress, size_t rdOffset, size_t rs1Address, size_t rs1Offset, size_t rs2Address, size_t rs2Offset) const;
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void emitMemCopyOp(mlir::StringRef opName,
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void emitMemCopyOp(pim_binary::Opcode opcode,
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size_t rdAddr,
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size_t rdOffset,
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size_t rs1Addr,
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size_t rs1Offset,
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size_t size,
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mlir::StringRef sizeFieldName = "size") const;
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void emitCommunicationOp(mlir::StringRef opName, size_t bufferAddr, size_t coreId, size_t size) const;
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void emitCommunicationOp(pim_binary::Opcode opcode, size_t bufferAddr, size_t coreId, size_t size) const;
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void emitMvmOp(size_t groupId, size_t rdAddr, size_t rdOffset, size_t rs1Addr, size_t rs1Offset) const;
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public:
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void emitBinaryVectorOp(pim_binary::Opcode opcode,
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mlir::Value output,
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mlir::Value lhs,
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mlir::Value rhs,
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size_t byteSize,
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const StaticValueKnowledge& knowledge) const;
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void emitUnaryVectorOp(pim_binary::Opcode opcode,
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mlir::Value output,
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mlir::Value input,
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size_t byteSize,
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const StaticValueKnowledge& knowledge,
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int32_t r2OrImm = 0,
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int32_t generic1 = 0) const;
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PimCodeGen(PimAcceleratorMemory& memory,
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llvm::raw_fd_ostream& coreBinary,
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PimInstructionWriter& instructionWriter,
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llvm::raw_fd_ostream* coreJson,
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const llvm::DenseMap<size_t, size_t>& emittedCoreIds)
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: memory(memory), coreBinaryStream(coreBinary), coreJsonStream(coreJson), emittedCoreIds(emittedCoreIds) {}
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: memory(memory), instructionWriter(instructionWriter), coreJsonStream(coreJson), emittedCoreIds(emittedCoreIds) {}
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uint32_t getEmittedInstructionCount() const { return emittedInstructionCount; }
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void setBatchLane(std::optional<unsigned> lane) { batchLane = lane; }
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llvm::FailureOr<int64_t> indexOf(mlir::Value value, const StaticValueKnowledge& knowledge) const {
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return memory.getIndexValue(value, knowledge);
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@@ -221,18 +235,7 @@ public:
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template <typename MVMTy>
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void codeGenMVMLikeOp(size_t mvmId, MVMTy mvmLikeOp, bool transposeMatrix, const StaticValueKnowledge& knowledge);
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void codeGenVVAddOp(pim::PimVVAddOp vvaddOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVVSubOp(pim::PimVVSubOp vvsubOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVVMulOp(pim::PimVVMulOp vvmulOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVVMaxOp(pim::PimVVMaxOp vvmaxOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVVDMulOp(pim::PimVVDMulOp vvdmulOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVAvgOp(pim::PimVAvgOp vavgOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVReluOp(pim::PimVReluOp vreluOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVTanhOp(pim::PimVTanhOp vtanhOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVSigmOp(pim::PimVSigmOp vsigmOp, const StaticValueKnowledge& knowledge) const;
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void codeGenVSoftmaxOp(pim::PimVSoftmaxOp vsoftmaxOp, const StaticValueKnowledge& knowledge) const;
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void codeGetGlobalOp(mlir::memref::GetGlobalOp getGlobalOp, const StaticValueKnowledge& knowledge) const;
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void codeGenTransposeOp(pim::PimTransposeOp transposeOp, const StaticValueKnowledge& knowledge) const;
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void codeGenTransposeOp(const CompiledTransposePlan& plan, const StaticValueKnowledge& knowledge) const;
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};
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OnnxMlirCompilerErrorCodes compileToPimCode(mlir::ModuleOp& moduleOpRef, std::string& outputDirName);
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