Add register reuse + peft scheduler cost model + Useless merger
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@@ -9,6 +9,7 @@
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#include "llvm/Support/JSON.h"
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#include "llvm/Support/raw_os_ostream.h"
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#include <array>
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#include <fstream>
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#include <limits>
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#include <optional>
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@@ -170,6 +171,7 @@ class PimCodeGen {
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const llvm::DenseMap<size_t, size_t>& emittedCoreIds;
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std::optional<unsigned> batchLane;
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mutable uint32_t emittedInstructionCount = 0;
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mutable std::array<std::optional<int32_t>, 256> scalarRegisterValues = {};
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size_t addressOf(mlir::Value value, const StaticValueKnowledge& knowledge) const {
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return memory.getValueAddress(value, knowledge, batchLane);
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@@ -177,6 +179,7 @@ class PimCodeGen {
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size_t remapCoreId(size_t coreId) const;
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void emitInstruction(const pim_binary::InstructionRecord& instruction) const;
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void updateScalarRegisterCache(const pim_binary::InstructionRecord& instruction) const;
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void genSetRegisterImmediateUnsigned(size_t registerNumber, size_t immediate) const;
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void setupRd(size_t rdAddress, size_t rdOffset) const;
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