NiccoloN
f1602c0550
Validate Operations / validate-operations (push) Has been cancelled
better deadlock report by pim simulator
73 lines
3.4 KiB
C++
73 lines
3.4 KiB
C++
#include "src/Accelerators/PIM/Compiler/PimCompilerOptions.hpp"
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#include "llvm/Support/ErrorHandling.h"
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#define DEBUG_TYPE "PimCompilerOptions"
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namespace onnx_mlir {
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llvm::cl::opt<PimEmissionTargetType> pimEmissionTarget(
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llvm::cl::desc("[Optional] Choose PIM-related target to emit (once selected it will cancel the other targets):"),
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llvm::cl::values(clEnumVal(EmitSpatial, "Lower model to spatial IR")),
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llvm::cl::values(clEnumVal(EmitPim, "Lower model to PIM IR")),
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llvm::cl::values(clEnumVal(EmitPimBufferized, "Lower model to PIM IR and bufferize it")),
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llvm::cl::values(clEnumVal(EmitPimCodegen, "Lower model to PIM IR and generate code for PIM")),
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llvm::cl::init(EmitPimCodegen),
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llvm::cl::cat(OnnxMlirOptions));
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llvm::cl::opt<PimMergeSchedulerType> pimMergeScheduler(
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"pim-merge-scheduler",
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llvm::cl::desc("Scheduler used by the Spatial merge-compute-nodes pass"),
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llvm::cl::values(clEnumValN(MergeSchedulerPeft, "peft", "Use PEFT scheduling")),
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llvm::cl::values(clEnumValN(MergeSchedulerDcp, "dcp", "Use the legacy DCP-inspired scheduler")),
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llvm::cl::init(MergeSchedulerPeft),
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llvm::cl::cat(OnnxMlirOptions));
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llvm::cl::opt<bool>
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pimOnlyCodegen("pim-only-codegen",
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llvm::cl::desc("Only generate code for PIM (assume input is already in bufferized PIM IR)"),
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llvm::cl::init(false),
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llvm::cl::cat(OnnxMlirOptions));
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llvm::cl::opt<bool> useExperimentalConvImpl("use-experimental-conv-impl",
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llvm::cl::desc("Use experimental implementation for convolution"),
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llvm::cl::init(false),
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llvm::cl::cat(OnnxMlirOptions));
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llvm::cl::opt<bool> pimEmitJson("pim-emit-json",
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llvm::cl::desc("Also emit per-core JSON instruction files alongside binary .pim files"),
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llvm::cl::init(false),
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llvm::cl::cat(OnnxMlirOptions));
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llvm::cl::opt<size_t>
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crossbarSize("crossbar-size", llvm::cl::desc("Width and height of a single crossbar"), llvm::cl::init(2));
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llvm::cl::opt<size_t>
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crossbarCountInCore("crossbar-count", llvm::cl::desc("Number of crossbars in each core"), llvm::cl::init(256));
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llvm::cl::opt<long> coresCount("core-count",
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llvm::cl::desc("Number of cores in the chip. Required for PIM compilation."),
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llvm::cl::init(-1));
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llvm::cl::opt<size_t> dcpCriticalWindowSize(
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"dcp-critical-window-size",
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llvm::cl::desc("Number of lowest-slack virtual nodes considered by each DCP coarsening iteration. "
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"Use 0 to run the legacy full-graph DCP analysis. Only used by the DCP scheduler."),
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llvm::cl::init(4000));
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llvm::cl::opt<bool>
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ignoreConcatError("ignore-concat-error",
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llvm::cl::desc("Ignore ConcatOp corner case: do not assert and do a simplification"),
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llvm::cl::init(false));
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bool hasExplicitPimCoreCount() { return coresCount.getNumOccurrences() != 0; }
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void verifyExplicitPimCoreCount() {
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if (!hasExplicitPimCoreCount())
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llvm::report_fatal_error("PIM compilation requires an explicit --core-count=<positive integer>");
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if (coresCount.getValue() <= 0)
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llvm::report_fatal_error("PIM compilation requires --core-count to be a positive integer");
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}
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} // namespace onnx_mlir
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